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dual low power, 8-/10-/12-/14-bit txdac digital-to-analog converters ad9114/ad9115/ad9116/ad9117 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features power dissipation @ 3.3 v, 20 ma output 191 mw @ 10 msps 232 mw @ 125 msps sleep mode: <3 mw @ 3.3 v supply voltage: 1.8 v to 3.3 v sfdr to nyquist 86 dbc @ 1 mhz output 85 dbc @ 10 mhz output ad9117 nsd @ 1 mhz output, 125 msps, 20 ma: ?162 dbc/hz differential current outputs: 4 ma to 20 ma 2 on-chip auxiliary dacs cmos inputs with single-port operation output common mode: adjustable 0 v to 1.2 v small footprint 40-lead lfcsp rohs-compliant package applications wireless infrastructures picocell, femtocell base stations medical instrumentation ultrasound transducer excitation portable instrumentation signal generators, arbitrary waveform generators general description the ad9114/ad9115/ad9116/ad9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (dacs) that provide a sample rate of 125 msps. these txdac? converters are optimized for the transmit signal path of commu- nication systems. all the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. the ad9114/ad9115/ad9116/ad9117 offer exceptional ac and dc performance and support update rates up to 125 msps. the flexible power supply operating range of 1.8 v to 3.3 v and low power dissipation of the ad9114/ad9115/ad9116/ad9117 make them well suited for portable and low power applications. product highlights 1. low power. dacs operate on a single 1.8 v to 3.3 v supply; total power consumption reduces to 225 mw at 100 msps. sleep and power-down modes are provided for low power idle periods. 2. cmos clock input. high speed, single-ended cmos clock input supports a 125 msps conversion rate. 3. easy interfacing to other components. adjustable output common mode from 0 v to 1.2 v allows for easy interfacing to other components that accept common-mode levels greater than 0 v.
ad9114/ad9115/ad9116/ad9117 rev. a | page 2 of 80 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 3 ? functional block diagram .............................................................. 4 ? specifications ..................................................................................... 5 ? dc specifications ......................................................................... 5 ? digital specifications ................................................................... 7 ? ac specifications .......................................................................... 8 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configurations and function descriptions ......................... 10 ? typical performance characteristics ........................................... 18 ? terminology .................................................................................... 31 ? theory of operation ...................................................................... 32 ? serial peripheral interface (spi) ................................................... 33 ? general operation of the serial interface ............................... 33 ? instruction byte .......................................................................... 33 ? serial interface port pin descriptions ..................................... 33 ? msb/lsb transfers..................................................................... 34 ? serial port operation ................................................................. 34 ? pin mode ..................................................................................... 34 ? spi register map ............................................................................. 35 ? spi register descriptions .............................................................. 36 ? digital interface operation ........................................................... 40 ? digital data latching and retimer section ............................ 41 ? estimating the overall dac pipeline delay........................... 42 ? reference operation .................................................................. 43 ? reference control amplifier .................................................... 43 ? dac transfer function ............................................................. 43 ? analog output ............................................................................ 44 ? self-calibration ........................................................................... 44 ? coarse gain adjustment ........................................................... 45 ? using the internal termination resistors ............................... 46 ? applications information .............................................................. 47 ? output configurations .............................................................. 47 ? differential coupling using a transformer ............................... 47 ? single-ended buffered output using an op amp ................ 47 ? differential buffered output using an op amp .................. 48 ? auxiliary dacs ........................................................................... 48 ? dac-to-modulator interfacing ................................................ 49 ? correcting for nonideal performance of quadrature modulators on the if-to-rf conversion ................................ 49 ? i/q channel gain matching ..................................................... 49 ? lo feedthrough compensation .............................................. 50 ? results of gain and offset correction .................................... 50 ? modifying the evaluation board to use the adl5370 on-board quadrature modulator ................................................................ 51 ? evaluation board schematics and artwork ................................ 52 ? schematics ................................................................................... 52 ? silkscreens ................................................................................... 60 ? bill of materials ............................................................................... 75 ? outline dimensions ....................................................................... 78 ? ordering guide .......................................................................... 78 ?
ad9114/ad9115/ad9116/ad9117 rev. a | page 3 of 80 revision history 3/09rev. 0 to rev. a changes to product title and general description section ....... 1 changes to figure 1 ........................................................................... 4 changed i otfs 2 ma to i xotfs 20 ma..................................... 5 changes to table 1 ............................................................................ 6 changed i otfs 2 ma to i xotfs 20 ma..................................... 7 changes to table 2 ............................................................................ 7 changed dvddio 1.8 v to dvddio 3.3 v table 3 and cvdd 3.3 v to cvdd 1.8 v table 4 ..................................... 8 changes to table 5 and table 6 ....................................................... 9 changes to table 7 .......................................................................... 10 changes to table 8 .......................................................................... 12 changes to table 9 .......................................................................... 14 changes to table 10 ........................................................................ 16 changes to typical performance characteristics section ......... 18 changes to theory of operation section and figure 84 ........... 32 added figure 85 to figure 88 renumbered seuentially ......... 34 changes to table 13 ........................................................................ 35 changes to table 14 ........................................................................ 36 changes to digital interface operation section and figure 89 figure 90 figure 91 figure 92 and figure 93 ............................ 40 changes to figure 94 digital data latching section and retimer section ............................................................................... 41 added reference operation section reference control amplifier section dac transfer function section figure 96 and table 17 ..................................................................................... 43 added analog output section ...................................................... 44 changes to auxiliary dacs section ............................................. 48 changes to dac to modulator interfacing section figure 107 and figure 108 ................................................................................. 49 added figure 111 to figure 133 .................................................... 52 added table 18 ................................................................................ 75 8/08revision 0: initial version
ad9114/ad9115/ad9116/ad9117 rev. a | page 4 of 80 functional block diagram i dac q dac aux1dac aux2dac band gap clock dist 10k? qr set 2k? ir set 2k? i ref 100a ir cm 60? to 260 ? qr cm 60? to 260 ? 62.5 ? 62.5 ? 62.5 ? 62.5 ? spi interface 1 into 2 interleaved data interface i data q data 1.8v ldo 1v ad9117 rlin ioutn ioutp rlip avdd avss rlqp qoutp qoutn rlqn db11 db10 db9 db8 dvddio dvss dvdd db7 db6 db5 db12 db13 (msb) cs/pwrdn sdio/format sclk/clkmd reset/pinmd refio fsadjq/auxq fsadji/auxi cmli db4 db3 db2 db1 (lsb) db0 dclkio cvdd clkin cvss cmlq 07466-001 figure 1.
ad9114/ad9115/ad9116/ad9117 rev. a | page 5 of 80 specifications dc specifications t min to t max , avdd = 3.3 v, dvdd = 1.8 v, dvddio = 3.3 v, cvdd = 3.3 v, i xoutfs = 20 ma, maximum sample rate, unless otherwise noted. table 1. parameter ad9114 ad9115 ad9116 ad9117 unit min typ max min typ max min typ max min typ max resolution 8 10 12 14 bits accuracy, avdd = dvddio = cvdd = 3.3 v differential nonlinearity (dnl) precalibration 0.02 0.06 0.4 1.4 lsb postcalibration 0.02 0.04 0.2 0.6 lsb integral nonlinearity (inl) precalibration 0.03 0.19 0.68 1.2 lsb postcalibration 0.03 0.07 0.42 0.6 lsb accuracy, avdd = dvddio = cvdd = 1.8 v differential nonlinearity (dnl) precalibration 0.02 0.08 0.5 1.8 lsb postcalibration 0.01 0.06 0.2 1.0 lsb integral nonlinearity (inl) precalibration 0.04 0.2 0.5 1.8 lsb postcalibration 0.02 0.1 0.3 1.1 lsb main dac outputs offset error ?1 +1 ?1 +1 ?1 +1 ?1 +1 mv gain error internal reference ?2 +2 ?2 +2 ?2 +2 ?2 +2 % of fsr full-scale output current 1 avdd = 3.3 v 2 8 20 2 8 20 2 8 20 2 8 20 ma avdd = 1.8 v 2 8 2 8 2 8 2 8 ma output common-mode level (8 ma cmlx pin) ?0.5 0 +1.2 ?0.5 0 +1.2 ?0.5 0 +1.2 ?0.5 0 +1.2 v output resistance 200 200 200 200 m crosstalk, q dac to i dac (f out = 30 mhz) 95 95 95 95 db crosstalk, q dac to i dac (f out = 60 mhz) 76 76 76 76 db main dac temperature drift offset 0 0 0 0 ppm/c gain 40 40 40 40 ppm/c reference voltage 25 25 25 25 ppm/c auxdac outputs resolution 10 10 10 10 bits full-scale output current (current sourcing mode) 125 125 125 125 a voltage output mode output compliance range (sourcing 1 ma) v ss v dd ? 0.25 v ss v dd ? 0.25 v ss v dd ? 0.25 v ss v dd ? 0.25 v output compliance range (sinking 1 ma) v ss + 0.25 v dd v ss + 0.25 v dd v ss + 0.25 v dd v ss + 0.25 v dd v output resistance in current output mode av ss to 1 v 1 1 1 1 m auxdac monotonicity guaranteed 10 10 10 10 bits
ad9114/ad9115/ad9116/ad9117 rev. a | page 6 of 80 parameter ad9114 ad9115 ad9116 ad9117 unit min typ max min typ max min typ max min typ max reference output internal reference voltage 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 v output resistance 10 10 10 10 k reference input voltage compliance avdd = 3.3 v 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 v avdd = 1.8 v 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 v input resistance external reference mode 1 1 1 1 m dac matching gain matching ?1 +1 ?1 +1 ?1 +1 ?1 +1 % of fsr analog supply voltages avdd 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 v cvdd 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 v digital supply voltages dvdd 1.7 1.9 1.7 1.9 1.7 1.9 1.7 1.9 v dvddio 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 v power consumption, avdd = dvddio = cvdd = 3.3 v f dac = 125 msps, if = 12.5 mhz 220 220 220 220 mw i avdd 55 55 55 55 ma i dvdd + i dvddio 10 10 10 10 ma i cvdd 3 3 3 3 ma power-down mode with clock 8.5 8.5 8.5 8.5 mw power-down mode no clock 3 3 3 3 mw power supply rejection ratio ?0.009 ?0.009 ?0.009 ?0.009 % fsr/v power consumption, avdd = dvddio = cvdd = 1.8 v f dac = 125 msps, if = 12.5 mhz 58 58 58 58 mw i avdd 24 24 24 24 ma i dvdd + i dvddio 8 8 8 8 ma i cvdd 2 2 2 2 ma power-down mode with clock 12 12 12 12 mw power-down mode no clock 850 850 850 850 w power supply rejection ratio ?0.007 ?0.007 ?0.007 ?0.007 % fsr/v operating range ?40 +25 +85 ?40 +25 +85 ?40 +25 +85 ?40 +25 +85 c 1 based on a 10 k external resistor.
ad9114/ad9115/ad9116/ad9117 rev. a | page 7 of 80 digital specifications t min to t max , avdd = 3.3 v, dvdd = 1.8 v, dvddio = 3.3 v, cvdd = 3.3 v, i xoutfs = 20 ma, maximum sample rate, unless otherwise noted. table 2. parameter min typ max unit dac clock input (clkin) v ih 2.1 3 v v il 0 0.9 v maximum clock rate 125 msps serial peripheral interface maximum clock rate (sclk) 25 mhz minimum pulse width high 20 ns minimum pulse width low 20 ns input data 1.8 v q channel or dclkio falling edge setup 0.25 ns hold 1.2 ns 1.8 v i channel or dclkio rising edge setup 0.13 ns hold 1.1 ns 3.3 v q channel or dclkio falling edge setup ?0.2 ns hold 1.5 ns 3.3 v i channel or dclkio rising edge setup ?0.2 ns hold 1.6 ns v ih 2.1 3 v v il 0 0.9 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 8 of 80 ac specifications t min to t max , avdd = 3.3 v, dvdd = 1.8 v, dvddio = 3.3 v, cvdd = 3.3 v, i xoutfs = 20 ma, maximum sample rate, unless otherwise noted. table 3. parameter ad9114 ad9115 ad9116 ad9117 unit min typ max min typ max min typ max min typ max spurious free dynamic range (sfdr) f dac = 125 msps, f out = 10 mhz 76 85 85 85 dbc f dac = 125 msps, f out = 50 mhz 55 55 55 55 dbc two tone intermodulation distortion (imd) f dac = 125 msps, f out = 10 mhz 81 81 81 82 dbc f dac = 125 msps, f out = 50 mhz 60 60 60 61 dbc noise spectral density (nsd), eight-tone, 500 khz tone spacing f dac = 125 msps, f out = 10 mhz ?132 ?143 ?153 ?157 dbc/hz f dac = 125 msps, f out = 50 mhz ?128 ?138 ?146 ?149 dbc/hz w-cdma adjacent channel leakage ratio (aclr), single carrier f dac = 61.44 msps, f out = 20 mhz ?78 ?78 ?78 ?78 dbc f dac = 122.88 msps, f out = 30 mhz ?80 ?80 ?80 ?80 dbc t min to t max , avdd = 1.8 v, dvdd = 1.8 v, dvddio = 1.8 v, cvdd = 1.8 v, i xoutfs = 8 ma, maximum sample rate, unless otherwise noted. table 4. parameter ad9114 ad9115 ad9116 ad9117 unit min typ max min typ max min typ max min typ max spurious free dynamic range (sfdr) f dac = 125 msps, f out = 10 mhz 73 76 76 76 dbc f dac = 125 msps, f out = 50 mhz 48 48 48 48 dbc two tone intermodulation distortion (imd) f dac = 125 msps, f out = 10 mhz 76 76 76 76 dbc f dac = 125 msps, f out = 50 mhz 50 50 50 50 dbc noise spectral density (nsd), eight-tone, 500 khz tone spacing f dac = 125 msps, f out = 10 mhz ?125 ?136 ?146 ?150 dbc/hz f dac = 125 msps, f out = 50 mhz ?117 ?127 ?135 ?138 dbc/hz w-cdma adjacent channel leakage ratio (aclr), single carrier f dac = 61.44 msps, f out = 20 mhz ?69 ?69 ?69 ?69 dbc f dac = 122.88 msps, f out = 30 mhz ?72 ?72 ?72 ?72 dbc
ad9114/ad9115/ad9116/ad9117 rev. a | page 9 of 80 absolute maximum ratings table 5. thermal resistance parameter rating avdd, dvddio, cvdd to avss, dvss, cvss ?0.3 v to +3.9 v dvdd to dvss ?0.3 v to +2.1 v avss to dvss, cvss ?0.3 v to +0.3 v dvss to avss, cvss ?0.3 v to +0.3 v cvss to avss, dvss ?0.3 v to +0.3 v refio, fsadjq, fsadji, cmlq, cmli to avss ?0.3 v to avdd + 0.3 v qoutp, qoutn, ioutp, ioutn, rlqp, rlqn, rlip, rlin to avss ?1.0 v to avdd + 0.3 v dbn 1 (msb) to d0 (lsb), cs , sclk, sdio, reset to dvss ?0.3 v to dvddio + 0.3 v clkin to cvss ?0.3 v to cvdd + 0.3 v junction temperature 125c storage temperature range ?65c to +150c table 6. package type ja jb 1 jc 1 unit 40-lead lfcsp (with no airflow movement) 29.8 19.0 3.4 c/w 1 these calculations are intended to represent the thermal performance of the indicated packages using a jedec multil ayer test board. do not assume the same level of thermal performance in actual applications without a careful inspection of the conditions in the application to determine that they are similar to those assumed in these calculations. esd caution 1 n stands for 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad9114/ad9115/ad9116/ad9117 rev. a | page 10 of 80 pin configurations and function descriptions pin 1 indicator 1 db5 2 db4 3 db3 4 db2 5 dvddio 6 dvss 7 dvdd 8 db1 9 db0 (lsb) 10 nc 23 24 25 26 27 28 29 30 22 21 1 1 n c 1 2 n c 1 3 n c 1 5 n c 1 7 c v d d 1 6 d c l k i o 1 8 c l k i n 1 9 c v s s 2 0 c m l q 1 4 n c 3 3 f s a d j i / a u x i 3 4 r e f i o 3 5 r e s e t / p i n m d 3 6 s c l k / c l k m d 3 7 s d i o / f o r m a t 3 8 c s / p w r d n 3 9 d b 7 ( m s b ) 4 0 d b 6 3 2 f s a d j q / a u x q 3 1 c m l i top view (not to scale) ad9114 07466-005 notes 1. nc = no connect 2. the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. qoutp rlqp avss avdd rlip ioutp ioutn rlin qoutn rlqn figure 2. ad9114 pin configuration table 7. ad9114 pin function descriptions pin no. mnemonic description 1 to 4 db[5:2] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo should not drive external loads. 8 db1 digital inputs 9 db0 (lsb) digital input (lsb). 10 to 15 nc no connect. these pins are not connected to the chip. 16 dclkio data input/output clock. clock used to qualify input data. 17 cvdd sampling clock supply voltage input (1.8 v to 3.3 v). cvdd must be dvdd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common-mode level. when the internal on-chip (qr cml ) is enabled, this pin is connected to the on-chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (qr cml ) is disabled, this pin is the common-mode load for q dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full-scal e current is sourced when all data bits are 0s. 23 qoutp q dac current output. full-scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog supply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full-scale curren t is sourced when all data bits are 1s.
ad9114/ad9115/ad9116/ad9117 rev. a | page 11 of 80 pin no. mnemonic description 29 ioutn complementary i dac current output. full-scal e current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutn externally. 31 cmli i dac output common-mode level. when the internal on-chip (ir cml ) is enabled, this pin is connected to the on-chip ir cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (ir cml ) is disabled, this pin is the common-mode load for i dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 32 fsadjq/auxq full-scale current output adjust (fsadj q). when the internal on chip (qr set ) is disabled, this pin is the full-scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external resistor is 4 k for 8 ma output current. auxiliary q dac output (auxq). when the internal on-chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi full-scale current output adjust (fsadj i). when the internal on-chip (ir set ) is disabled, this pin is the full-scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external re sistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on-chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal reference is disabled. provides a 1.0 v reference output when in internal reference mode (a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logi c low (pull-down to dvss) sets the part in spi mode. pulse reset high to reset the spi registers to their default values. a logic high (pull-up to dvddio) p uts the device into pin mode (pinmd). 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock input for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pu lse 0 to 1 to edge trigger the internal retimer, see the retimer section. 37 sdio/format serial port input/output (sdio). in spi mode, th is pin is the bidirectional data line for the serial port. format pin (format). in pin mode, format determines the data format of digital data. a logic low (pull-down to dvss) selects the binary input data format. a logic high (pull-up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power-down (pwrdn). in pin mode, a logic high (pull-up to dvddio) powers down the device, except for the spi port. 39 db7 (msb) digital input (msb). 40 db6 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 rev. a | page 12 of 80 pin 1 indicator 1 db7 2 db6 3 db5 4 db4 5 dvddio 6 dvss 7 dvdd 8 db3 9 db2 10 db1 23 qoutp 24 rlqp 25 avss 26 avdd 27 rlip 28 ioutp 29 ioutn 30 rlin 22 qoutn 21 rlqn 1 1 d b 0 ( l s b ) 1 2 n c 1 3 n c 1 5 n c 1 7 c v d d 1 6 d c l k i o 1 8 c l k i n 1 9 c v s s 2 0 c m l q 1 4 n c 3 3 f s a d j i / a u x i 3 4 r e f i o 3 5 r e s e t / p i n m d 3 6 s c l k / c l k m d 3 7 s d i o / f o r m a t 3 8 c s / p w r d n 3 9 d b 9 ( m s b ) 4 0 d b 8 3 2 f s a d j q / a u x q 3 1 c m l i top view (not to scale) ad9115 07466-004 notes 1. nc = no connect 2 . the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. figure 3. ad9115 pin configuration table 8. ad9115 pin function description pin no. mnemonic description 1 to 4 db[7:4] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo should not drive external loads. 8 to 10 db[3:1] digital inputs. 11 db0 (lsb) digital input (lsb). 12 to 15 nc no connect. these pins are not connected to the chip. 16 dclkio data input/output clock. clock used to qualify input data. 17 cvdd sampling clock supply voltage input (1.8 v to 3.3 v). cvdd must be dvdd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common-mode level. when the internal on-chip (qr cml ) is enabled, this pin is connected to the on-chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (qr cml ) is disabled, this pin is the common-mode load for q dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full-scal e current is sourced when all data bits are 0s. 23 qoutp q dac current output. full-scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog supply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full-scale curren t is sourced when all data bits are 1s. 29 ioutn complementary i dac current output. full-scal e current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutn externally.
ad9114/ad9115/ad9116/ad9117 rev. a | page 13 of 80 pin no. mnemonic description 31 cmli i dac output common-mode level. when the internal on-chip (ir cml ) is enabled, this pin is connected to the on-chip ir cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (ir cml ) is disabled, this pin is the common-mode load for i dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 32 fsadjq/auxq full-scale current output adjust (fsadj q). when the internal on chip (qr set ) is disabled, this pin is the full- scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external re sistor is 4 k for 8 ma output current. auxiliary q dac output (auxq). when the internal on-chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi full-scale current output adjust (fsadj i). when the internal on-chip (ir set ) is disabled, this pin is the full-scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external re sistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on-chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal reference is disabled. provides a 1.0 v reference output when in internal reference mode (a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logi c low (pull-down to dvss) sets the part in spi mode. pulse reset high to reset the spi registers to their default values. a logic high (pull-up to dvddio) p uts the device into pin mode (pinmd). 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock input for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pu lse 0 to 1 to edge trigger the internal retime, see the retimer section. 37 sdio/format serial port input/output (sdio). in spi mode, th is pin is the bidirectional data line for the serial port. format pin (format). in pin mode, format determines th e data format of digital data. a logic low (pull-down to dvss) selects the binary input data format. a logic high (pull-up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power-down (pwrdn). in pin mode, a logic high (pull-up to dvddio) powers down the device, except for the spi port. 39 db9 (msb) digital input (msb). 40 db82 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 rev. a | page 14 of 80 pin 1 indicator 1 db9 2 db8 3 db7 4 db6 5 dvddio 6 dvss 7 dvdd 8 db5 9 db4 10 db3 23 qoutp 24 rlqp 25 avss 26 avdd 27 rlip 28 ioutp 29 ioutn 30 rlin 22 qoutn 21 rlqn 1 1 d b 2 1 2 d b 1 1 3 d b 0 ( l s b ) 1 5 n c 1 7 c v d d 1 6 d c l k i o 1 8 c l k i n 1 9 c v s s 2 0 c m l q 1 4 n c 3 3 f s a d j i / a u x i 3 4 r e f i o 3 5 r e s e t / p i n m d 3 6 s c l k / c l k m d 3 7 s d i o / f o r m a t 3 8 c s / p w r d n 3 9 d b 1 1 ( m s b ) 4 0 d b 1 0 3 2 f s a d j q / a u x q 3 1 c m l i top view (not to scale) ad9116 notes 1. nc = no connect 2 . the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. 07466-003 figure 4. ad9116 pin configuration table 9. ad9116 pin function descriptions pin no. mnemonic description 1 to 4 db[9:6] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo should not drive external loads. 8 to 12 db[5:1] digital inputs. 13 db0 (lsb) digital input (lsb). 14, 15 nc no connect. these pins are not connected to the chip. 16 dclkio data input/output clock. clock used to qualify input data. 17 cvdd sampling clock supply voltage input (1.8 v to 3.3 v). cvdd must be dvdd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common-mode level. when the internal on-chip (qr cml ) is enabled, this pin is connected to the on-chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (qr cml ) is disabled, this pin is the common-mode load for q dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full-scal e current is sourced when all data bits are 0s. 23 qoutp q dac current output. full-scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog supply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full-scale curren t is sourced when all data bits are 1s. 29 ioutn complementary i dac current output. full-scal e current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutn externally.
ad9114/ad9115/ad9116/ad9117 rev. a | page 15 of 80 pin no. mnemonic description 31 cmli i dac output common-mode level. when the internal on-chip (ir cml ) is enabled, this pin is connected to the on-chip ir cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (ir cml ) is disabled, this pin is the common mode load for i dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 32 fsadjq/auxq full-scale current output adjust (fsadj q). when the internal on chip (qr set ) is disabled, this pin is the full- scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external re sistor is 4 k for 8 ma output current. auxiliary q dac output (auxq). when the internal on-chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi full-scale current output adjust (fsadj i). when the internal on-chip (ir set ) is disabled, this pin is the full-scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external re sistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on-chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal reference is disabled. provides a 1.0 v reference output when in internal reference mode (a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logi c low (pull-down to dvss) sets the part in spi mode. pulse reset high to reset the spi registers to their default values. a logic high (pull-up to dvddio) p uts the device into pin mode (pinmd). 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock input for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pu lse 0 to 1 to edge trigger the internal retime, see the retimer section. 37 sdio/format serial port input/output (sdio). in spi mode, th is pin is the bidirectional data line for the serial port. format pin (format). in pin mode, format determines the data format of digital data. a logic low (pull-down to dvss) selects the binary input data format. a logic high (pull-up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power-down (pwrdn). in pin mode, a logic high (pull-up to dvddio) powers down the device, except for the spi port. 39 db11 (msb) digital input (msb). 40 db10 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 rev. a | page 16 of 80 pin 1 indicator 1 db11 2 db10 3 db9 4 db8 5 dvddio 6 dvss 7 dvdd 8 db7 9 db6 10 db5 23 qoutp 24 rlqp 25 avss 26 avdd 27 rlip 28 ioutp 29 ioutn 30 rlin 22 qoutn 21 rlqn 1 1 d b 4 1 2 d b 3 1 3 d b 2 1 5 d b 0 ( l s b ) 1 7 c v d d 1 6 d c l k i o 1 8 c l k i n 1 9 c v s s 2 0 c m l q 1 4 d b 1 3 3 f s a d j i / a u x i 3 4 r e f i o 3 5 r e s e t / p i n m d 3 6 s c l k / c l k m d 3 7 s d i o / f o r m a t 3 8 c s / p w r d n 3 9 d b 1 3 ( m s b ) 4 0 d b 1 2 3 2 f s a d j q / a u x q 3 1 c m l i top view (not to scale) ad9117 07466-002 notes 1. the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. figure 5. ad9117 pin configuration table 10. ad9117 pin function descriptions pin no. mnemonic description 1 to 4 db[11:8] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo should not drive external loads. 8 to 14 db[7:1] digital inputs. 15 db0 (lsb) digital input (lsb). 16 dclkio data input/output clock. clock used to qualify input data. 17 cvdd sampling clock supply voltage input (1.8 v to 3.3 v). cvdd must be dvdd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common-mode level. when the internal on-chip (qr cml ) is enabled, this pin is connected to the on-chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (qr cml ) is disabled, this pin is the common-mode load for q dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full-scal e current is sourced when all data bits are 0s. 23 qoutp q dac current output. full-scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog supply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full-scale curren t is sourced when all data bits are 1s. 29 ioutn complementary i dac current output. full-scal e current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutn externally.
ad9114/ad9115/ad9116/ad9117 rev. a | page 17 of 80 pin no. mnemonic description 31 cmli i dac output common-mode level. when the internal on-chip (ir cml ) is enabled, this pin is connected to the on-chip ir cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (ir cml ) is disabled, this pin is the common-mode load for i dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 32 fsadjq/auxq full-scale current output adjust (fsadj q). when the internal on chip (qr set ) is disabled, this pin is the full- scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external re sistor is 4 k for 8 ma output current. auxiliary q dac output (auxq). when the internal on-chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi full-scale current output adjust (fsadj i). when the internal on-chip (ir set ) is disabled, this pin is the full-scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external re sistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on-chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal reference is disabled. provides a 1.0 v reference output when in internal reference mode (a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logi c low (pull-down to dvss) sets the part in spi mode. pulse reset high to reset the spi registers to their default values. a logic high (pull-up to dvddio) p uts the device into pin mode (pinmd). 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock input for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pu lse 0 to 1 to edge trigger the internal retime, see the retimer section. 37 sdio/format serial port input/output (sdio). in spi mode, th is pin is the bidirectional data line for the serial port. format pin (format). in pin mode, format determines the data format of digital data. a logic low (pull-down to dvss) selects the binary input data format. a logic high (pull-up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power-down (pwrdn). in pin mode, a logic high (pull-up to dvddio) powers down the device, except for the spi port. 39 db13 (msb) digital input (msb). 40 db12 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 rev. a | page 18 of 80 typical performance characteristics avdd, dvdd, dvddio, cvdd = 1.8 v, i xoutfs = 8 ma, maximum sample rate (125 msps), unless otherwise noted. 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?2.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration inl (lsb) 07466-006 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?2.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration inl (lsb) 07466-009 figure 6. ad9117 precalibration inl at 1.8 v, 8 ma (dvdd = 1.8 v) figure 9. ad9117 postcalibration inl at 1.8 v, 8 ma (dvdd = 1.8 v) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?2.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration dnl (lsb) 07466-007 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?2.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration dnl (lsb) 07466-010 figure 7. ad9117 precalibration dnl at 1.8 v, 8 ma (dvdd = 1.8 v) figure 10. ad9117 postcalibration dnl at 1.8 v, 8 ma (dvdd = 1.8 v) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration inl (lsb) 0 7466-008 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration inl (lsb) 0 7466-011 figure 8. ad9117 precalibration inl at 3.3 v, 20 ma (dvdd = 1.8 v) figure 11. ad9117 postcalibration inl at 3.3 v, 20 ma (dvdd = 1.8 v)
ad9114/ad9115/ad9116/ad9117 rev. a | page 19 of 80 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration dnl (lsb) 0 7466-012 figure 12. ad9117 precalibration dnl at 3.3 v, 20 ma 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration inl (lsb) 0 7466-013 figure 13. ad9116 precalibration inl at 1.8 v, 8 ma 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration dnl (lsb) 0 7466-014 figure 14. ad9116 precalibration dnl at 1.8 v, 8 ma 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration dnl (lsb) 0 7466-015 figure 15. ad9117 postcalibration dnl at 3.3 v, 20 ma 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration inl (lsb) 0 7466-016 figure 16. ad9116 postcalibration inl at 1.8 v, 8 ma 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration dnl (lsb) 0 7466-017 figure 17. ad9116 postcalibration dnl at 1.8 v, 8 ma
ad9114/ad9115/ad9116/ad9117 rev. a | page 20 of 80 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration inl (lsb) 0 7466-018 figure 18. ad9116 precalibration inl at 3.3 v, 20 ma 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.5 ?0.4 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration dnl (lsb) 0 7466-019 figure 19. ad9116 precalibration dnl at 3.3 v, 20 ma 0.25 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.25 ?0.20 0 128 256 384 512 640 768 896 1024 code precalibration inl (lsb) 0 7466-020 figure 20. ad9115 precalibration inl at 1.8 v, 8 ma 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration inl (lsb) 0 7466-021 figure 21. ad9116 postcalibration inl at 3.3 v, 20 ma 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.5 ?0.4 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration dnl (lsb) 07466-022 figure 22. ad9116 postcalibration dnl at 3.3 v, 20 ma 0.25 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.25 ?0.20 0 128 256 384 512 640 768 896 1024 code postcalibration inl (lsb) 07466-023 figure 23. ad9115 postcalibration inl at 1.8 v, 8 ma
ad9114/ad9115/ad9116/ad9117 rev. a | page 21 of 80 0.08 0.06 0.02 0.04 ?0.02 0 ?0.04 ?0.06 ?0.08 0 128 256 384 512 640 768 896 1024 code precalibration dnl (lsb) 07466-024 figure 24. ad9115 precalibration dnl at 1.8 v, 8 ma 0.25 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.25 ?0.20 0 128 256 384 512 640 768 896 1024 code precalibration inl (lsb) 0 7466-025 figure 25. ad9115 precalibration inl at 3.3 v, 20 ma 0.08 0.06 0.02 0.04 ?0.02 0 ?0.04 ?0.06 ?0.08 0 128 256 384 512 640 768 896 1024 code precalibration dnl (lsb) 07466-026 figure 26. ad9115 precalibration dnl at 3.3 v, 20 ma 0.08 0.06 0.02 0.04 ?0.02 0 ?0.04 ?0.06 ?0.08 0 128 256 384 512 640 768 896 1024 code postcalibration dnl (lsb) 07466-027 figure 27. ad9115 postcalibration dnl at 1.8 v, 8 ma 0.25 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.25 ?0.20 0 128 256 384 512 640 768 896 1024 code postcalibration inl (lsb) 0 7466-028 figure 28. ad9115 postcalibration inl at 3.3 v, 20 ma 0.08 0.06 0.02 0.04 ?0.02 0 ?0.04 ?0.06 ?0.08 0 128 256 384 512 640 768 896 1024 code postcalibration dnl (lsb) 07466-029 figure 29. ad9115 postcalibration dnl at 3.3 v, 20 ma
ad9114/ad9115/ad9116/ad9117 rev. a | page 22 of 80 0.035 0.015 0.025 0.005 0 ?0.005 ?0.015 ?0.025 ?0.035 0 32 64 96 128 160 192 224 256 code precalibration inl (lsb) 07466-030 figure 30. ad9114 precalibration inl at 1.8 v, 8 ma 0.025 0.020 0.015 0.010 0.005 0 ?0.005 ?0.010 ?0.015 ?0.020 ?0.025 0 32 64 96 128 160 192 224 256 code precalibration dnl (lsb) 07466-031 figure 31. ad9114 precalibration dnl at 1.8 v, 8 ma 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 0 32 64 96 128 160 192 224 256 code precalibration inl (lsb) 07466-032 figure 32. ad9114 precalibration inl at 3.3 v, 20 ma 0.035 0.015 0.025 0.005 0 ?0.005 ?0.015 ?0.025 ?0.035 0 32 64 96 128 160 192 224 256 code postcalibration inl (lsb) 07466-033 figure 33. ad9114 postcalibration inl at 1.8 v, 8 ma 0.025 0.020 0.015 0.010 0.005 0 ?0.005 ?0.010 ?0.015 ?0.020 ?0.025 0 32 64 96 128 160 192 224 256 code postcalibration dnl (lsb) 07466-034 figure 34. ad9114 postcalibration dnl at 1.8 v, 8 ma 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 0 32 64 96 128 160 192 224 256 code postcalibration inl (lsb) 07466-035 figure 35. ad9114 postcalibration inl at 3.3 v, 20 ma
ad9114/ad9115/ad9116/ad9117 rev. a | page 23 of 80 0.025 0.020 0.015 0.010 0.005 0 ?0.005 ?0.010 ?0.015 ?0.020 ?0.025 0 32 64 96 128 160 192 224 256 code precalibration dnl (lsb) 07466-036 figure 36. ad9114 precalibration dnl at 3.3 v, 20 ma ? 124 ?130 ?136 ?142 ?148 ?154 ?160 0 102030405 f out (mhz) nsd (dbc) ad9117 ad9116 ad9115 ad9114 0 07466-137 figure 37. nsd at 8 ma vs. f out , 1.8 v ?160 ? 136 ?139 ?142 ?145 ?148 ?151 ?154 ?157 0 102030 5 15253540455055 07466-201 f out (mhz) nsd (dbm/hz) ?40c +85c +25c figure 38. ad9117 nsd at three temperatures 8 ma vs. f out , 1.8 v 0.025 0.020 0.015 0.010 0.005 0 ?0.005 ?0.010 ?0.015 ?0.020 ?0.025 0326496128 code 160 192 224 256 postcalibration dnl (lsb) 07466-039 figure 39. ad9114 postcalibration dnl at 3.3 v, 20 ma ?166 ?160 ?154 ?148 ?142 ?136 ?130 ? 124 0 102030 5 15253540455055 07466-200 f out (mhz) nsd (dbc) ad9117 ad9116 ad9115 ad9114 figure 40. nsd at 20 ma vs. f out , 3.3 v ?160 ? 136 ?139 ?142 ?145 ?148 ?151 ?154 ?157 0 102030 5 15253540455055 07466-202 f out (mhz) nsd (dbm/hz) ?40c +85c +25c figure 41. ad9117 nsd at three temperatures 8 ma vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 24 of 80 ?166 ?160 ?154 ?148 ?142 ?136 ? 130 0 5 10 15 20 25 30 35 40 45 50 55 f out (mhz) nsd (dbc) 1.8v, 4ma 1.8v, 8ma 07466-142 figure 42. ad9117 nsd at two output currents vs. f out , 1.8 v 07466-090 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 figure 43. ad9117 two tone spectrum at 1.8 v 50 60 70 80 90 5 101520253035404550 f out (mhz) imd (dbc) ad9117 ad9116 ad9115 ad9114 0 7466-144 figure 44. all imd 8 ma vs. f out , 1.8 v ?166 ?160 ?154 ?148 ?142 ?136 ? 130 0 5 10 15 20 25 30 35 40 45 50 55 f out (mhz) nsd (dbc) 3.3v, 20ma 3.3v, 8ma 3.3v, 4ma 07466-145 figure 45. ad9117 nsd at three output currents vs. f out , 3.3 v 07466-091 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 figure 46. ad9117 two tone spectrum at 3.3 v 54 66 60 72 84 78 96 90 5 101520253035404550 ad9117 ad9116 ad9115 ad9114 f out (mhz) imd (dbc) 0 7466-147 figure 47. all imd 20 ma vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 25 of 80 48 84 78 72 66 60 54 5 101520253035404550 07466-195 f out (mhz) imd (dbc) ?40c +85c +25c figure 48. ad9117 imd at three temperatures 8 ma vs. f out , 1.8 v 45 50 55 60 65 70 75 80 85 90 5 101520253035404550 0db ?3db ?6db 07466-092 f out (mhz) imd (dbc) figure 49. ad9117 imd at three digital signal levels vs. f out , 1.8 v 50 56 62 68 74 80 86 5 101520253035404550 f out (mhz) imd (dbc) 4ma 8ma 07466-150 figure 50. ad9117 imd at two output currents vs. f out , 1.8 v 63 90 87 84 81 78 75 72 69 66 5 101520253035404550 07466-196 f out (mhz) imd (dbc) ?40c +85c +25c figure 51. ad9117 imd at three temperatures 20 ma vs. f out , 3.3 v 55 60 65 70 75 80 85 90 5 101520253035404550 0db ?3db ?6db 07466-093 f in (mhz) imd (dbc) figure 52. ad9117 imd at three digital signal levels vs. f out , 3.3 v 56 62 68 74 80 92 86 5 101520253035404550 f out (mhz) imd (dbc) 4ma 20ma 8ma 07466-153 figure 53. ad9117 imd at three output currents vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 26 of 80 07466-088 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 figure 54. ad9117 singe tone spectrum, 1.8 v 40 50 60 70 80 90 0 102030405060 f out (mhz) sfdr (dbc) ad9117 ad9116 ad9115 ad9114 07466-155 figure 55. sfdr at 8 ma vs. f out , 1.8 v 42 48 54 60 66 72 78 84 90 0 5 10 15 20 25 30 35 40 45 50 55 60 f out (mhz) sfdr (dbc) 40c 25c 85c 07466-156 figure 56. ad9117 sfdr at three temperatures 8 ma vs. f out , 1.8 v 07466-089 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 figure 57. ad9117 singe tone spectrum, 3.3 v 54 60 66 72 84 78 90 96 0 102030405060 f out (mhz) sfdr (dbc) ad9117 ad9116 ad9115 ad9114 07466-158 figure 58. ad9117 sfdr at 20 ma vs. f out , 3.3 v 56 62 68 74 80 86 92 98 0 5 10 15 20 25 30 35 40 45 50 55 60 f out (mhz) sfdr (dbc) 40c 25c 85c 07466-159 figure 59. ad9117 sfdr at three temperatures 8 ma vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 27 of 80 42 50 58 66 74 82 90 98 0 5 10 15 20 25 30 35 40 45 50 55 60 07466-094 f out (mhz) sfdr (dbc) 0db ?6db ?3db figure 60. ad9117 sfdr at three digital signal levels vs. f out , 1.8 v 42 48 54 60 66 72 78 84 90 96 0 10203040506 f out (mhz) sfdr (dbc) 4ma 8ma 0 07466-161 figure 61. ad9117 sfdr at two currents vs. f out , 1.8 v center 22.90mhz total carrier power ?12.17dbm/7.87420mhz ref carrier power ?12.17dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. ?12.17dbm 5.000mhz 3.840mhz ?77.40 ?89.56 ?78.68 ?90.84 2. ?80.85dbm 10.00mhz 3.840mhz ?78.90 ?91.06 ?78.27 ?90.43 15.00mhz 3.840mhz ?78.02 ?90.18 ?70.99 ?83.15 10db/di v vbw 300khz offset freq integ bw dbc dbm dbc lower upper dbm span 38.84mhz res bw 30khz sweep 126ms (601pts) step 2db ac coupled: unspecified below 20mhz input att 8.00db 07466-162 figure 62. ad9117 aclr one-carrier, 1.8 v 50 58 66 74 82 90 98 0 5 10 15 20 25 30 35 40 45 50 55 60 07466-095 f out (mhz) sfdr (dbc) 0db ?6db ?3db figure 63. ad9117 sfdr at three digital signal levels vs. f out ., 3.3 v 42 48 54 60 66 72 78 84 90 96 0 102030405060 f out (mhz) sfdr (dbc) 4ma 8ma 20ma 07466-164 figure 64. ad9117 sfdr at three currents vs. f out , 3.3v center 22.90mhz 10db/di v vbw 300khz span 38.84mhz step 2db input att 8.00db total carrier power ?12.17dbm/7.87420mhz ref carrier power ?12.17dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. ?12.17dbm 5.000mhz 3.840mhz ?77.40 ?89.56 ?78.68 ?90.84 2. ?80.85dbm 10.00mhz 3.840mhz ?78.90 ?91.06 ?78.27 ?90.43 15.00mhz 3.840mhz ?78.02 ?90.18 ?70.99 ?83.15 offset freq integ bw dbc dbm dbc lower upper res bw 30khz sweep 126ms (601pts) ac coupled: unspecified below 20mhz 07466-165 figure 65. ad9117 aclr one-carrier, 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 28 of 80 ?78 ?72 ?66 ? 60 15 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-166 figure 66. ad9117 one-carrier w-cdma first aclr vs. f out , 1.8 v ?80 ?74 ?68 ? 62 15 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-167 figure 67. ad9117 one-carrier w-cdma second aclr vs. f out , 1.8 v ?80 ?74 ?68 ? 62 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-168 figure 68. ad9117 one-carrier w-cdma third aclr vs. f out , 1.8 v ?78 ?72 ?66 ? 60 15 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-169 figure 69. ad9117 one-carrier w-cdma first aclr vs. f out , 3.3 v ?80 ?74 ?68 ? 62 15 25 35 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-170 figure 70. ad9117 one-carrier w-cdma second aclr vs. f out , 3.3 v ?80 ?74 ?68 ? 62 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-171 figure 71. ad9117 one-carrier w-cdma third aclr vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 29 of 80 center 22.90mhz 10db/di v vbw 300khz span 38.84mhz step 2db input att 8.00db total carrier power ?15.23dbm/7.87420mhz ref carrier power ?18.09dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. ?18.09dbm 5.000mhz 3.840mhz ?72.11 ?90.24 ?71.97 ?90.09 2. ?18.40dbm 10.00mhz 3.840mhz ?72.98 ?91.10 ?72.55 ?90.68 15.00mhz 3.840mhz ?69.93 ?88.05 ?72.30 ?90.42 offset freq integ bw dbc dbm dbc lower upper dbm res bw 30khz sweep 126ms (601pts) ac coupled: unspecified below 20mhz 07466-172 figure 72. ad9117 aclr two-carrier, 1.8 v ?74 ?68 ?62 ?56 ? 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-173 figure 73. ad9117 two-carrier w-cdma first aclr vs. f out , 1.8 v ?74 ?68 ?62 ?56 ? 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-174 figure 74. ad9117 two-carrier w-cdma second aclr vs. f out , 1.8 v center 22.90mhz 10db/di v vbw 300khz span 38.84mhz step 2db input att 8.00db total carrier power ?15.23dbm/7.87420mhz ref carrier power ?18.09dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. ?18.09dbm 5.000mhz 3.840mhz ?72.11 ?90.24 ?71.97 ?90.09 2. ?18.40dbm 10.00mhz 3.840mhz ?72.98 ?91.10 ?72.55 ?90.68 15.00mhz 3.840mhz ?69.93 ?88.05 ?72.30 ?90.42 offset freq integ bw dbc dbm dbc lower upper dbm res bw 30khz sweep 126ms (601pts) ac coupled: unspecified below 20mhz 07466-175 figure 75. ad9117 aclr two-carrier, 3.3 v ?74 ?68 ?62 ?56 ? 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-176 figure 76. ad9117 two-carrier w-cdma first aclr vs. f out , 3.3 v ?74 ?68 ?62 ?56 ? 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-177 figure 77. ad9117 two-carrier w-cdma second aclr vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 30 of 80 ?74 ?68 ?56 ?62 ? 50 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 0 7466-178 ?74 ?68 ?56 ?62 ? 50 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 0 7466-181 figure 78. ad9117 two-carrier w-cdma third aclr vs. f out , 1.8 v figure 81. ad9117 two-carrier w-cdma third aclr vs. f out , 3.3 v 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?1.0 ?0.8 0 code auxdac inl (lsb) 128 256 384 512 640 768 896 1024 0 7466-044 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.5 ?0.4 0 code auxdac dnl (lsb) 128 256 384 512 640 768 896 1024 0 7466-047 figure 79. ad9114/ad9115/ad9116/ad9117 auxdac dnl figure 82. ad9114/ad9115/ad9116/ad9117 auxdac inl cvdd dvdd avdd @ 4ma out avdd @ 8ma out total current @ 4ma out total current @ 8ma out 40 30 20 10 0 0 20 40 60 80 100 120 140 f dac (mhz) supply current (ma) 07466-048 0 10 20 30 40 50 60 70 80 0 20406080100120140 f dac (mhz) cur r ent ( m a) cvdd dvdd avdd @ 20ma out total current @ 20ma out total current @ 8ma out total current @ 4ma out avdd @ 8ma out avdd @ 4ma out 0 7466-183 figure 80. ad9114/ad9115/ad9116/ad9117 supply current vs. f dac , 1.8 v figure 83. ad9114/ad9115/ad9116/ad9117supply current vs. f dac , 3.3 v
ad9114/ad9115/ad9116/ad9117 rev. a | page 31 of 80 terminology linearity error or integral nonlinearity (inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error offset error is the deviation of the output current from the ideal of zero. for i outp , the 0 ma output is expected when the inputs are all 0. for i outn , the 0 ma output is expected when all inputs are set to 1. gain error gain error is the difference between the actual and the ideal output span. the actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. output compliance range the output compliance range is the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change from the ambient value (25c) to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full- scale range per degree celsius (ppm fsr/c). for reference drift, the drift is reported in parts per million per degree celsius (ppm/c). power supply rejection power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. spurious free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. it is expressed as a percentage (%) or in decibels (db). signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels (db). adjacent channel leakage ratio (aclr) aclr is the ratio in decibels relative to the carrier (dbc) between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two-part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected.
ad9114/ad9115/ad9116/ad9117 rev. a | page 32 of 80 theory of operation i dac q dac aux1dac aux2dac band gap clock dist 10k? qr set 2k? ir set 2k? i ref 100a ir cm 60? to 260 ? qr cm 60? to 260 ? 62.5 ? 62.5 ? 62.5 ? 62.5 ? spi interface 1 into 2 interleaved data interface i data q data 1.8v ldo 1v ad9117 rlin ioutn ioutp rlip avdd avss rlqp qoutp qoutn rlqn db11 db10 db9 db8 dvddio dvss dvdd db7 db6 db5 db12 db13 (msb) cs/pwrdn sdio/format sclk/clkmd reset/pinmd refio fsadjq/auxq fsadji/auxi cmli db4 db3 db2 db1 (lsb) db0 dclkio cvdd clkin cvss cmlq 07466-050 figure 84. simplified block diagram figure 84 shows a simplified block diagram of the ad9114/ ad9115/ad9116/ad9117 that consists of two dacs, digital control logic, and a full-scale output current control. each dac contains a pmos current source array capable of providing a maximum of 20 ma. the arrays are divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 of an msb current source. the remaining lsbs are binary weighted fractions of the current sources of the middle bits. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of the main dacs (that is, >200 m). the current sources are switched to one or the other of the two output nodes (i outp or i outn ) via pmos differential current switches. the switches are based on the architecture that was pioneered in the ad976x family, with further refinements to reduce distortion contributed by the switching transient. this switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital i/o sections of the ad9114/ad9115/ ad9116/ad9117 have separate power supply inputs (avdd and dvddio) that can operate independently over a 1.8 v to 3.3 v range. the core digital section requires 1.8 v. an optional on-chip ldo is provided for dvddio supplies greater than 1.8 v, or the 1.8 v can be supplied directly through dvdd. a 1.0 f bypass capacitor at dvdd (pin 7) is required when using the ldo. the core is capable of operating at a rate of up to 125 msps. it consists of edge-triggered latches and the segment decoding logic circuitry. the analog section includes pmos current sources, associated differential switches, a 1.0 v band gap voltage reference, and a reference control amplifier. each dac full-scale output current is regulated by the reference control amplifier and can be set from 4 ma to 20 ma via an external resistor, xr set , connected to its full-scale adjust pin (fsadjx). the external resistor, in combination with both the reference control amplifier and voltage reference, v refio , sets the reference current, i xref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i xoutfs , is 32 i xref . optional on-chip xr set resistors are provided that can be programmed between a nominal value of 1.6 k to 8 k (4 ma to 20 ma i xoutfs , respectively). the ad9114/ad9115/ad9116/ad9117 provide the option of setting the output common mode to a value other than agnd via the output common-mode pin (cmli and cmlq). this facilitates directly interfacing the output of the ad9114/ad9115/ad9116/ ad9117 to components that require common-mode levels greater than 0 v.
ad9114/ad9115/ad9116/ad9117 rev. a | page 33 of 80 serial peripheral interface (spi) the serial port of the ad9114/ad9115/ad9116/ad9117 is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and micro- processors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad9114/ad9115/ad9116/ad9117. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the serial interface port of the ad9114/ ad9115/ad9116/ad9117 is configured as a single i/o pin on the sdio pin. general operation of the serial interface there are two phases to a communication cycle on the ad9114/ ad9115/ad9116/ad9117. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9114/ad9115/ ad9116/ad9117, coinciding with the first eight sclk rising edges. in phase 2, the instruction byte provides the serial port controller of the ad9114/ad9115/ad9116/ad9117 with infor- mation regarding the data transfer cycle. the phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9114/ad9115/ad9116/ad9117. a logic 1 on pin 35 (reset/pinmd), followed by a logic 0, resets the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the spi port. if the spi port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9114/ ad9115/ad9116/ad9117 and the system controller. phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. using a multibyte transfer is the preferred method. single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the information shown in table 11 . table 11. msb lsb db7 db6 db5 db4 db3 db2 db1 db0 r/ w n1 n0 a4 a3 a2 a1 a0 r/ w (bit 7 of the instruction byte) determines whether a read or a write data transfer occurs after the instruction byte write. logic 1 indicates a read operation. logic 0 indicates a write operation. n1 and n0 (bit 6 and bit 5 of the instruction byte) determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table 12 . table 12. byte transfer count n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes a4, a3, a2, a1, and a0 (bit 4, bit 3, bit 2, bit 1, and bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. for multi- byte transfers, this address is the starting byte address. the following register addresses are generated internally by the ad9114/ad9115/ad9116/ad9117 based on the lsbfirst bit (register 0x00, bit 6). serial interface port pin descriptions sclkserial clock the serial clock pin is used to synchronize data to and from the ad9114/ad9115/ad9116/ad9117 and to run the internal state machines. the sclk maximum frequency is 20 mhz. all data input to the ad9114/ad9115/ad9116/ad9117 is registered on the rising edge of sclk. all data is driven out of the ad9114/ ad9115/ad9116/ad9117 on the falling edge of sclk. cs chip select an active low input starts and gates a communications cycle. it allows more than one device to be used on the same serial commu- nications lines. the sdio/format pin reaches a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdioserial data i/o the sdio pin is used as a bidirectional data line to transmit and receive data.
ad9114/ad9115/ad9116/ad9117 rev. a | page 34 of 80 msb/lsb transfers the serial port of the ad9114/ad9115/ad9116/ad9117 can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the lsbfirst bit (register 0x00, bit 6). the default is msb first (lsbfirst = 0). when lsbfirst = 0 (msb first), the instruction and data bytes must be written from the most significant bit to the least significant bit. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow in order from a high address to a low address. in msb first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communications cycle. when lsbfirst = 1 (lsb first), the instruction and data bytes must be written from the least significant bit to the most significant bit. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. if the msb first mode is active, the serial port controller data address of the ad9114/ad9115/ad9116/ad9117 decrements from the data address written toward 0x00 for multibyte i/o operations. if the lsb first mode is active, the serial port controller address increments from the data address written toward 0x1f for multibyte i/o operations. serial port operation the serial port configuration of the ad9114/ad9115/ad9116/ ad9117 is controlled by register 0x00. it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register can occur during the middle of the communications cycle. care must be taken to compensate for this new configu- ration for the remaining bytes of the current communications cycle. the same considerations apply to setting the software reset bit (register 0x00, bit 5). all registers are set to their default values except register 0x00, which remains unchanged. use of single-byte transfers or initiating a software reset is recommended when changing serial port configurations to prevent unexpected device behavior. r/wn1n0a4a3 a2a1a0d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle cs scl k sdio 07466-291 figure 85. serial register interface timing, msb first write r/wn1n0a4a3 a2a1a0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle sclk sdio sdo 07466 -290 cs figure 86. serial register interface timing, msb first read a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle scl k sdio 0 7466-289 cs figure 87. serial register interface timing, lsb first write instruction cycle data transfer cycle sclk sdio sdo a0 a1 a2 a3 a4 n0 n1 r/w d1 0 d2 0 d7 n d6 n d5 n d4 n d0 07466-288 cs figure 88. serial register interface timing, lsb first read pin mode the ad9114/ad9115/ad9116/ad9117 can also be operated without ever writing to the serial port. with reset/pinmd (pin 35) tied high, the sclk pin becomes clkmd to provide for clock mode control (see the retimer section), the sdio pin becomes format and selects the input data format, and the cs /pwrdn pin serves to power down the device. operation is otherwise exactly as defined by the default register values in tabl e 13 ; therefore, external resistors at fsadji and fsadjq are needed to set the dac currents, and both dacs are active. this is also a convenient quick checkout mode. dac currents can be externally adjusted in pin mode by sourcing or sinking currents at the fsadji/auxi and fsadjq/auxq pins, as desired, with the fixed resistors installed. an op amp output with appropriate series resistance is one of many possibilities. this has the same effect as changing the resistor value. place at least 10 k resistors in series right at the dac to guard against accidental short circuits and noise modulation. the refio pin can be adjusted 25% in a similar manner, if desired.
ad9114/ad9115/ad9116/ad9117 rev. a | page 35 of 80 spi register map table 13. name addr default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spi control 0x00 0x00 reserved lsbfirst reset lngins reserved power-down 0x01 0x40 ldooff ldostat pwrdn q dacoff i dacoff qclkoff iclkoff extref data control 0x02 0x34 twos reserved ifirst irising simulbit dci_en dcosgl dcodbl i dac gain 0x03 0x00 reserved i dacgain[5:0] irset 0x04 0x00 irseten reserved irset[5:0] ircml 0x05 0x00 ircmlen reserved ircml[5:0] q dac gain 0x06 0x00 reserved q dacgain[5:0] qrset 0x07 0x00 qrseten reserved qrset[5:0] qrcml 0x08 0x00 qrcmlen reserved qrcml[5:0] auxdac q 0x09 0x00 qauxdac[7:0] aux ctlq 0x0a 0x00 qauxen qauxrng[1:0] qauxofs[2:0] qauxdac[9:8] auxdac i 0x0b 0x00 iauxdac[7:0] aux ctli 0x0c 0x00 iauxen iauxrng[ 1:0] iauxofs[2:0] iauxdac[9:8] reference resistor 0x0d 0x00 reserved rref[5:0] cal control 0x0e 0x00 preldq preldi calselq calseli calclk divsel[2:0] cal memory 0x0f 0x00 calstatq calstati reserved calmemq[1:0] calmemi[1:0] memory address 0x10 0x00 reserved memaddr[5:0] memory data 0x11 0x34 reserved memdata[5:0] memory r/w 0x12 0x00 calrstq calrsti calen smemwr smemrd uncalq uncali clkmode 0x14 0x00 clkmodeq[1:0] search ing reacquire clkmoden clkmodei[1:0] version 0x1f 0x09 version[7:0]
ad9114/ad9115/ad9116/ad9117 rev. a | page 36 of 80 spi register descriptions reading these registers returns previously written values for all defined register bits, unless otherwise noted. table 14. register address bit name description spi control 0x00 6 lsbfirst 0 (defa ult): msb first per spi standard. 1: lsb first per spi standard. note that the user must always chan ge the lsb/msb order in single-byte instructions to avoid erratic behavior due to bit order errors. 5 reset executes software reset of spi and controllers, reloads default register values, except register 0x00. 1: set software reset; write 0 on the next (or any following) cycle to release reset. 4 lngins 0 (default): the spi inst ruction word uses a 5-bit address. 1: the spi instruction word uses a 13-bit address. power down 0x01 7 ldooff 0 (default): ldo voltage regulator on. 1: turns core ldo voltage regulator off. 6 ldostat 0: indicates that the core ldo voltage regulator is off. 1 (default): indicates that the core ldo voltage regulator is on. 5 pwrdn 0 (default): all analog, digital circuitry and spi logic are powered on. 1: powers down all analog and digital circuitry, except for spi logic. 4 q dacoff 0 (default): turns on q dac output current. 1: turns off q dac output current. 3 i dacoff 0 (default): turns on i dac output current. 1: turns off i dac output current. 2 qclkoff 0 (default): turns on q dac clock. 1: turns off q dac clock. 1 iclkoff 0 (default): turns on i dac clock. 1: turns off i dac clock. 0 extref 0 (default): turns on internal voltage reference. 1: powers down the internal voltage reference (external reference required). data control 0x02 7 twos 0 (default): unsigned binary input data format. 1: twos complement input data format. 5 ifirst 0: pairing of dataq first of pair on data input pads. 1(default): pairing of datai firs t of pair on data input pads (default). 4 irising 0: q data latched on dclkio rising edge. 1(default): i data latched on dclkio rising edge (default). 3 simulbit 0 (default): allows simultan eous input and output enable on dclkio. 1: disallows simultaneous input and output en able on dclkio. 2 dci_en controls the use of the dclkio pad for the data clock input. 0: data clock input disabled. 1(default): data clock input enabled. 1 dcosgl controls the use of the dclkio pad for the data clock output. 0 (default): data clock output disabled. 1: data clock output enabled; regular strength driver. 0 dcodbl controls the use of the dclkio pad for the data clock output. 0 (default): dcodbl data clock output disabled. 1: dcodbl data clock output enabled; paralleled with dcosgl for 2 drive current. i dac gain 0x03 5:0 i dacgain[5:0] dac i fine gain adjustment; alters the full-scale current, as shown in figure 99 . default idacgain = 0x00.
ad9114/ad9115/ad9116/ad9117 rev. a | page 37 of 80 register address bit name description irset 0x04 7 irseten 0 (default): ir set resistor value for i channel is set by an external resistor connected to the fadji/auxi pin. nominal value for this external resistor is 4 k. 1: enables the on-chip ir set value to be changed for i channel. 5:0 irset[5:0] changes the value of the on-chip ir set resistor; this scales the full-scale current of the dac in ~0.25 db steps twos complement (nonlinear), see figure 98 . 000000 (default): ir set = 2 k. 011111: ir set = 4 k. 100000: ir set = 1.6 k. 111111: ir set = 2 k. ircml 0x05 7 ircmlen 0 (default): ir cml resistor value for the i channel is set by an external resistor connected to cmli pin. recommended value for this external resistor is 0 . 1: enables on-chip ir cml adjustment for i channel. 5:0 ircml[5:0] changes the value of the on-chip ir cml resistor for i channel; this adjusts the common-mode level of the dac output stage. 000000 (default): ir cml = 60 . 100000: ir cml = 160 . 111111: ir cml = 260 . q dac gain 0x06 5:0 q dacgain[5:0] dac q fine gain adjustment; alters the full-scale current, as shown in figure 99 . default qdacgain = 0x00. qrset 0x07 7 qrseten 0 (default): qr set resistor value for q channel is set by an external resistor connected to fadji/auxi pin. nominal value for this external resistor is 4 k. 1: enables on-chip qr set adjustment for q channel. 5:0 qrset[5:0] changes the value of the on-chip qr set resistor; this scales the full-scale current of the dac in ~0.25 db steps twos complement (nonlinear). 000000 (default): qr set = 2 k. 011111: qr set = 4 k. 100000: qr set = 1.6 k. 111111: qr set = 2 k. qrcml 0x08 7 qrcmlen 0 (default): qr cml resistor value for the q channel is set by an external resistor connected to cmlq pin. recommended value for this external resistor is 0 . 1: enables on-chip qr cml adjustment. 5:0 qrcml[5:0] changes the value of the on-chip qr cml resistor for q channel; this adjusts the common-mode level of the dac output stage. 000000 (default): qr cml = 60 . 100000: qr cml = 160 . 111111: qr cml = 260 . auxdac q 0x09 7:0 qauxdac[7:0] auxdac q output voltage adjustment word lsbs. 0x3ff: sets auxdac q output to full scale. 0x200: sets auxdac q output to midscale. 0x000 (default): sets auxdac q output to bottom of scale. aux ctlq 0x0a 7 qauxen 0 (default): auxdac q output disabled. 1: enables auxdac q output. 6:5 qauxrng[1:0] 00 (default): sets auxdac q output voltage range to 2 v. 01: sets auxdac q output voltage range to 1.5 v. 10: sets auxdac q output voltage range to 1.0 v. 11: sets auxdac q output voltage range to 0.5 v. 4:2 qauxofs[2:0] 000 (default): sets auxdac q top of range to 1.0 v. 001: sets auxdac q top of range to 1.5 v. 010: sets auxdac q top of range to 2.0 v. 011: sets auxdac q top of range to 2.5 v. 100: sets auxdac q top of range to 2.9 v. 1:0 qauxdac[9:8] auxdac q output voltage adjustment word msbs (default = 00).
ad9114/ad9115/ad9116/ad9117 rev. a | page 38 of 80 register address bit name description auxdac i 0x0b 7:0 iauxdac[7:0] auxdac i output voltage adjustment word lsbs. 0x3ff: sets auxdac i output to full scale. 0x200: sets auxdac i output to midscale. 0x000 (default): sets auxdac i output to bottom of scale. aux ctli 0x0c 7 iauxen 0 (default): auxdac i output disabled. 1: enables auxdac i output. 6:5 iauxrng[1:0] 00 (default): sets au xdac i output voltage range to 2 v. 01: sets auxdac i output voltage range to 1.5 v. 10: sets auxdac i output voltage range to 1.0 v. 11: sets auxdac i output voltage range to 0.5 v. 4:2 iauxofs[2:0] 000 (default): sets auxdac i top of range to 1.0 v. 001: sets auxdac i top of range to 1.5 v. 010: sets auxdac i top of range to 2.0 v. 011: sets auxdac i top of range to 2.5 v. 100: sets auxdac i top of range to 2.9 v. 1:0 iauxdac[9:8] aux dac i output voltage adjustment word msbs (default = 00). reference resistor 0x0d 5:0 rref[5:0] permits an adjustment of the on-chip reference voltage and output at refio (see figure 97 ) twos complement. 000000 (default): sets the value of r ref to 10 k, v ref = 1.0 v. 011111: sets the value of r ref to 12 k, v ref = 1.2 v. 100000: sets the value of r ref to 8 k, v ref = 0.8 v. 111111: sets the value of r ref to 10 k, v ref = 1.0 v. cal control 0x0e 7 preldq 0 (default): preloads q dac calibration reference set to 32. 1: preloads q dac calibration reference set by user (cal address 1). 6 preldi 0 (default): preloads i dac calibration reference set to 32. 1: preloads i dac calibration reference set by user (cal address 1). 5 calselq 0 (default): q dac self-calibration done. 1: selects q dac self-calibration. 4 calseli 0 (default): i dac self-calibration done. 1: selects i dac self-calibration. 3 calclk 0 (default): calibration clock disabled. 1: calibrates clock enabled. 2:0 divsel[2:0] calibration clock divide ratio from dac clock rate. 000 (default): divide by 256. 001: divide by 128. 110: divide by 4. 111: divide by 2. cal memory 0x0f 7 calstatq 0 (default): q dac calibration in progress. 1: calibration of q dac complete. 6 calstati 0 (default): i dac calibration in progress. 1: calibration of i dac complete. 3:2 calmemq[1:0] status of q dac calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user-calibrated. 1:0 calmemi[1:0] status of i dac calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user-calibrated. memory address 0x10 5:0 memaddr[5:0] addre ss of static memory to be accessed. memory data 0x11 5:0 memdata[5:0] data for static memory access.
ad9114/ad9115/ad9116/ad9117 rev. a | page 39 of 80 register address bit name description memory r/w 0x12 7 calrstq 0 (default): no action. 1: clears calstatq. 6 calrsti 0 (default): no action. 1: clears calstati. 4 calen 0 (default): no action. 1: initiates device self-calibration. 3 smemwr 0 (default): no action. 1: writes to static memo ry (calibration coefficients). 2 smemrd 0 (default): no action. 1: reads from static memo ry (calibration coefficients). 1 uncalq 0 (default): no action. 1: resets q dac calibration co efficients to default (uncalibrated). 0 uncali 0 (default): no action. 1: resets i dac calibration co efficients to default (uncalibrated). clkmode 0x14 7:6 clkmodeq[1:0] depending on clkmoden bit setting, these two bits reflect the phase relationship between dclkio and clkin, as described in table 16 . if clkmoden = 0, read only; reports the clock phase chosen by the retime. if clkmoden = 1, read/write; value in this register sets q clock phases; force if needed to better synchronize the dacs (see the retimer section). 4 searching datapath retimer status bit. 0 (default): clock relationship established. 1: indicates that the internal datapath retimer is searching for clock relationship (device output is not usable while this bit is high). 3 reacquire edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship. 2 clkmoden 0 (default): clkmodei/clkmodeq values co mputed by the two retimers and read back in clkmodei[1:0] and clkmodeq[1:0]. 1: clkmode values set in clkmodei[1:0] override both i and q retimers. 1:0 clkmodei[1:0] depending on clkmoden bit setting, these two bits reflect the phase relationship between dclkio and clkin, as described in table 16 . if clkmoden = 0, read only; reports the clock phase chosen by the retimer. if clkmoden = 1, read/write; value in this register sets i clock phases; force if needed to better synchronize the dacs (see the retimer section). version 0x1f 7:0 version[7:0] hardware version of the device. this register is set to 0x09 for the latest version of the device.
ad9114/ad9115/ad9116/ad9117 rev. a | page 40 of 80 digital interface operation dclkio za b c d e f g h i data z b d f q data a c e g 07466-053 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] digital data for the i and q dacs is supplied over a single parallel bus (db[n:0], where n is 7 for the ad9114, is 9 for the ad9115, is 11 for the ad9116, and 13 for the ad9117) accompanied by a qualifying clock (dclkio). the i and q data are provided to the chip in an interleaved double data rate (ddr) format. the maximum guaranteed data rate is 250 msps with a 125 mhz clock. the order of data pairing and the sampling edge selection is user programmable using the ifirst and irising data control bits, resulting in four possible timing diagrams. these timing diagrams are shown in figure 89 , figure 90 , figure 91 , and figure 92 . figure 91. timing diagram with ifirst = 1, irising = 0 dclkio notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] z a b c d e f g h i data z b d f q data y a c e 07466-051 dclkio za b c d e f g h i data y a c e q data z b d f 07466-054 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] figure 89. timing diagram with ifirst = 0, irising = 0 figure 92. timing diagram with ifirst = 1, irising = 1 dclkio za b c d e f g h i data y a c e q data x z b d 07466-052 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] ideally, the rising and falling edges of the clock fall in the center of the keep-in window formed by the setup and hold times, t s and t h . refer to table 2 for setup and hold times. a detailed timing diagram is shown in figure 93 . dclkio db[n:0] t s t h t s t h 07466-055 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. figure 90. timing diagram with ifirst = 0, irising = 1 figure 93. setup and hold times for all input modes in addition to the different timing modes listed in table 2 , the input data can also be presented to the device in either unsigned binary or twos complement format. the format type is chosen via the twos data control bit.
ad9114/ad9115/ad9116/ad9117 rev. a | page 41 of 80 3 2 1 0 d-ff d-ff 4 d-ff d-ff d-ff or dclkio-int clkin-int db[n:0] (input) to dac core i out i out delay1 delay2 delay1 retimer-clk ie ie oe dclkio (input/output) clkin (input) notes d-ffs: 0: rising or falling edge triggered for i or q data. 1, 2, 3, 4: rising edge triggered. retimer-clk 07466-056 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. figure 94. simplified diagram of ad9114/ad9115/ad9116/ad9117 timing digital data latching and retimer section the ad9114/ad9115/ad9116/ad9117 have two clock inputs, dclkio and clkin. the clkin is the analog clock whose jitter affects dac performance, and the dclkio is a digital clock from an fpga that needs to have a fixed relationship with the input data to ensure that the data is sampled correctly by the flip-flops on the pads. figure 94 is a simplified diagram of the entire data capture system in the ad9114/ad9115/ad9116/ad9117. the double data rate input data (db[n:0], where n is 7 for the ad9114, is 9 for the ad9115, is 11 for the ad9116, and 13 for the ad9117) is latched at the pads/pins either on the rising edge or the falling edge of the dclkio-int clock, as determined by irising, bit 4 of spi address 0x02. bit 5 of spi address 0x02, ifirst, determines which channel data is latched first (that is, i or q). the captured data is then retimed to the internal clock (clkin-int) in the retimer block before being sent to the final analog dac core (d-ff 4), which controls the current steering output switches. all delay blocks depicted in figure 94 are non-inverting, and any wires without an explicit delay block can be assumed to have no delay. only one channel is shown in figure 94 with the data pads (db[n:0], where n is 7 for the ad9114, is 9 for the ad9115, is 11 for the ad9116, and 13 for the ad9117) serving as double data rate pads for both channels. the default pinmd and spi settings are ie high (closed) and oe low (open). these settings are enabled when reset/pinmd (pin 35) is held high. in this mode, the user has to supply both dclkio and clkin. in pinmd, it is also recommended that the dclkio and the clkin be in phase for proper functioning of the dac, which can easily be ensured by tying the pins together on the pcb. if the user can access the spi, setting bit 2 of spi address 0x02, dcien, to logic low causes the clkin to be used as the dclkio also. setting bit 1 or bit 0 of spi address 0x02, dcosgl or dcodbl, to logic high allows the user to get a dclkio output from the clkin input for use in the users pcb system. it is strongly recommended that dcien dcosgl high, or dcien dcodbl high not be used, even though the device may appear to function correctly. similarly, dcosgl and dcodbl should not be set to logic high simultaneously. retimer he d114/d11/d11/d11 ha e an internal data retimer circuit that compares the clki-i and dclkio-i clocks and depending on their phase relationship selects a retimer clock reimer-clk to safel transfer data from the dclkio used at the chips input interface to the clki used to clock the analog dc cores d-ff 4 he retimer selects one of the three phases shon in figure he retimer is controlled the clkmode spi its as is shon in ale 1 1/2 period 1/4 period 1/2 period data clock retimer-clks 180 90 270 07466-057 figure 95. retimer-clk phases note that, in most cases, more than one retimer phase works and, in such cases, the retimer arbitrarily picks one phase that works. the retimer cannot pick the best or safest phase. if the user has a working knowledge of the exact phase relationship between dclkio and clkin (and thus dclkio-int and clkin-int because the delay is approximately the same for both clocks and eual to dela1), then the retimer can be forced to this phase with clkmoden = 1, as described in table 15 and the following paragraphs.
ad9114/ad9115/ad9116/ad9117 rev. a | page 42 of 80 table 15. timer register list bit name description clkmodeq[1:0] q datapath retimer clock selected output. valid after the searching bit goes low. searching high indicates that the internal datapath retimer is searching for the clock relationship (dac is not usable until it is low again). reacquire changing this bit from 0 to 1 causes the datapath retimer circui t to reacquire the clock relationship. clkmoden 0: uses the clkmodei/clkmodeq values (as comput ed by the two internal retimers) for i and q clocking. 1: uses the clkmode value set in clkmodei[1:0] to override the bits for both the i and q retimers (that is, force the retimer) . clkmodei[1:0] i datapath retimer clock selected output. valid after searchin g goes low. if clkmoden = 1, a value written to this register overrides both i and q automatic retimer values. table 16. clkmodei/clkmodeq details clkmodei[1:0]/clkmodeq[1:0] dclkio-to-clkin phase relationship retimer-clk selected 00 0 to 90 phase 2 01 90 to 180 phase 3 10 180 to 270 phase 3 11 270 to 360 phase 1 when reset is pulsed high and then returns low (the part is in spi mode), the retimer runs and automatically selects a suitable clock phase for the retimer-clk within 128 clock cycles. the spi searching bit, bit 4 of spi address 0x14, returns to low, indicating that the retimer has locked and the part is ready for use. the reacquire bit, bit 3 of spi address 0x14, can be used to reinitiate phase detection in the i and q retimers at any time. clkmodeq[1:0] and clkmodei[1:0] bits of spi address 0x14 provide readback for the values picked by the internal phase detectors in the retimer (see table 16 ). to force the two retimers (i and q) to pick a particular phase for the retimer clock (they must both be forced to the same value), clkmoden, bit 2 of the spi address 0x14, should be set high and the required phase value is written into clkmodei[1:0]. for example, if the dclkio and the clkin are in phase to first order, the user could safely force the retimers to pick phase 2 for the retimer-clk. this forcing function may be useful for synchronizing multiple devices. in pin mode, it is expected that the user tie clkin and dclkio together. the device has a small amount of programmable func- tionality using the now unused spi pins (sclk, sdio, and cs ). if the two chip clocks are tied together, the sclk pin can be tied to ground, and the chip uses a clock for the retimer that is 180 out of phase with the two input clocks (that is, phase 2, which is the safest and best option). the chip has an additional option in pin mode when the redefined sclk pin is high. use this mode if using pin mode, but clkin and dclkio are not tied together (that is, not in phase). holding sclk high causes the internal clock detector to use the phase detector output to determine which clock to use in the retimer (that is, select a suitable retimer-clk phase). the action of taking sclk high causes the internal phase detector to reexamine the two clocks and determine the relative phase. whenever the user wants to reevaluate the relative phase of the two clocks, the sclk pin can be taken low and then high again. estimating the overall dac pipeline delay dac pipeline latency is affected by the phase of the retimer- clk that is selected. if latency is critical to the system and must be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time. consider the case in which dclkio clkin (that is, in phase), and the retimer-clk is forced to phase 2. assume that irising is 1 (that is, q data is latched on the rising edge and i data is latched on the falling edge). then the latency to the output for the i channel is three clock cycles (d-ff 1, d-ff 3, and d-ff 4, but not d-ff 2, because it is latched on the half clock cycle or 180). the latency to the output for the q channel from the time the falling edge latches it at the pads in d-ff 0 is 2.5 clock cycles ( clock cycle to d-ff 1, 1 clock cycle to d-ff 3, and 1 clock cycle to d-ff 4). this latency for the ad9114/ad9115/ ad9116/ad9117 is case specific and needs to be calculated based on the retimer-clk phase that is automatically selected or manually forced.
ad9114/ad9115/ad9116/ad9117 rev. a | page 43 of 80 reference operation the ad9114/ad9115/ad9116/ad9117 contains an internal 1.0 v band gap reference. the internal reference can be disabled by setting bit 0 (extref) of the power-down register (address 0x01) through the spi interface. to use the internal reference, decouple the refio pin to avss with a 0.1 f capacitor, enable the internal reference, and clear bit 0 of the power-down register (address 0x01) through the spi interface. note that this is the default configuration. the internal reference voltage is present at refio. if the voltage at refio is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 na must be used to avoid loading the reference. an example of the use of the internal reference is shown in figure 96 . current scaling x32 ad9114/ad9115/ ad9116/ad9117 i dac or q dac 07466-218 i xoutfs xr set 0.1f refio i xref avss fsadjx v bg 1.0v + ? figure 96. internal reference configuration refio serves as either an input or an output, depending on whether the internal or an external reference is used. tabl e 17 summarizes the reference operation. table 17. reference operation reference mode refio pin register setting internal connect 0.1 f capacitor register 0x01, bit 0 = 0 (default) external apply external capacitor register 0x01, bit 0 = 1 (for power saving) an external reference can be used in applications requiring tighter gain tolerances or lower temperature drift. in addition, a variable external voltage reference can be used to implement a method for gain control of the dac output. recommendations when using an external reference apply the external reference to the refio pin. the internal reference can be directly overdriven by the external reference, or the internal reference can be powered down to save power consumption. the external 0.1 f compensation capacitor on refio is not required unless specified by the external voltage reference manufacturer. the input impedance of refio is 10 k when the internal reference is powered up and 1 m when it is powered down. reference control amplifier the ad9114/ad9115/ad9116/ad9117 contains a control amplifier that regulates the full-scale output current, i xoutfs . the control amplifier is configured as a v-i converter, as shown in figure 96 . the output current, i xref , is determined by the ratio of the v refio and an external resistor, xr set , as stated in equation 4 (see the dac transfer function section). i xref is mirrored to the segmented current sources with the proper scale factor to set i xoutfs , as stated in equation 3 (see the dac transfer function section). the control amplifier allows a 2.5:1 adjustment span of i xoutfs from 8 ma to 20 ma by setting i xref between 250 a and 625 a (xr set between 1.6 k and 4 k). the wide adjustment span of i xoutfs provides several benefits. the first relates directly to the power dissipation of the ad9114/ad9115/ad9116/ad9117, which is proportional to i xoutfs (see the dac transfer function section). the second benefit relates to the ability to adjust the output over a 8 db range with 0.25 db steps, which is useful for controlling the transmitted power. the small signal bandwidth of the reference control amplifier is approximately 500 khz. this allows the device to be used for low frequency, small signal multiplying applications. dac transfer function the ad9114/ad9115/ad9116/ad9117 provides two differential current outputs, ioutp/ioutn and qoutp/ qoutn. ioutp and qoutp provide a near full-scale current output, i xoutfs , when all bits are high (that is, dac code = 2 n ? 1, where n = 8, 10, 12, or 14 for the ad9114, ad9115, ad9116, and ad9117, respectively), while ioutn and qoutn, the complementary outputs, provide no current. the current outputs appearing at the positive dac outputs, ioutp and qoutp, and at the negative dac outputs, ioutn and qoutn, are a function of both the input code and i xoutfs and can be expressed as follows: ioutp = ( idac code /2 n ) i ioutfs (1) qoutp = ( qdac code /2 n ) i qoutfs ioutn = ((2 n ? 1) ? idac code )/2 n i ioutfs (2) qoutn = ((2 n ? 1) ? qdac code )/2 n i qoutfs where: idac code and qdac code = 0 to 2 n ? 1 (that is, decimal representation). i ioutfs and i qoutfs are functions of the reference currents, i iref and i qref , respectively, which are nominally set by a reference voltage, v refio , and external resistors, ir set and qr set, respectively. i ioutfs and i qoutfs can be expressed as follows: i ioutfs = 32 i iref (3) i qoutfs = 32 i qref where: i iref = v refio / ir set (4) i qref = v refio /qr set
ad9114/ad9115/ad9116/ad9117 rev. a | page 44 of 80 or i ioutfs = 32 v refio / ir set (5) i qoutfs = 32 v refio / qr set a differential pair (ioutp/ioutn or qoutp/qoutn) typically drives a resistive load directly or via a transformer. if dc coupling is required, the differential pair (ioutp/ioutn or qoutp/qoutn) should be connected to matching resistive loads, xr load , that are tied to analog common, avss. the single- ended voltage output appearing at the positive and negative nodes is v ioutp = ioutp ir load (6) v qoutp = qoutp qr load v ioutn = ioutn ir load (7) v qoutn = qoutn qr load to achieve the maximum output compliance of 1 v at the nominal 20 ma output current, ir load = qr load must be set to 50 . substituting the values of ioutp, ioutn, i xref , and v idiff can be expressed as v idiff = {(2 idac code ? (2 n ? 1))/2 n } (32 v refio / ir set ) ir load (8) equation 8 highlights some of the advantages of operating the ad9114/ad9115/ad9116/ad9117 differentially. first, the differential operation helps cancel common-mode error sources associated with ioutp and ioutn, such as noise, distortion, and dc offsets. second, the differential code-dependent current and subsequent voltage, v idiff , is twice the value of the single-ended voltage output (that is, v ioutp or v ioutb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single-ended output (v ioutp and v ioutn ) or differential output of the ad9114/ad9115/ad9116/ ad9117 can be enhanced by selecting temperature tracking resistors for xr load and xr set because of their ratiometric relationship, as shown in equation 8. analog output the complementary current outputs in each dac, ioutp/ ioutn and qoutp/qoutn, can be configured for single- ended or differential operation. ioutp/ioutn and qoutp/ qoutn can be converted into complementary single-ended voltage outputs, v ioutp and v ioutn as well as v qoutp and v qoutn via a load resistor, xr load , as described in the dac transfer function section by equation 6 through equation 8. the differential voltages, v idiff and v qdiff , existing between v ioutp and v ioutn , and v qoutp and v qoutn , can also be converted to a single-ended voltage via a transformer or a differential amplifier configuration. the ac performance of the ad9114/ad9115/ad9116/ad 9117 is optimum and is specified using a differential transformer-coupled output in which the voltage swing at ioutp and ioutn is limited to 0.5 v. the distortion and noise performance of the ad9114/ad9115/ad9116/ad9117 can be enhanced when it is configured for differential operation. the common-mode error sources of both ioutp/ioutn and qoutp/qoutn can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. this is due to the first- order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). because the output currents of ioutp/ioutn and qoutp/qoutn are complementary, they become additive when processed differentially. self-calibration the ad9114/ad9115/ad9116/ad9117 have a self-calibration feature that improves the dnl of the device. performing a self- calibration on the device improves device performance in low frequency applications. the device performance in applications where the analog output frequencies are above 5 mhz are generally influenced more by dynamic device behavior than by dnl and, in these cases, self-calibration is unlikely to produce measurable benefits. the calibration clock frequency is equal to the dac clock divided by the division factor chosen by the divsel value. each calibration clock cycle is between 32 and 2048 dac input clock cycles, depending on the value of divsel[2:0] (register 0x0e, bits[2:0]). the frequency of the calibration clock should be between 0.5 mhz and 4 mhz for reliable calibrations. best results are obtained by setting divsel[2:0] to produce a calibration clock frequency between these values. separate self-calibration hardware is included for each dac. the dacs can be self- calibrated individually or simultaneously. to perform a device self-calibration, use the following procedure: 1. write 0x00 to register 0x12. this ensures that the uncali and uncalq bits (bit 1 and bit 0) are reset. 2. set up a calibration clock between 0.5 mhz and 4 mhz using divsel[2:0], and then enable the calibration clock by setting the calclk bit (register 0x0e, bit 3). 3. select the dac(s) to self-calibrate by setting either bit 4 (calseli) for the i dac and/or bit 5 (calselq) for the q dac in register 0x0e. note that each dac contains independent calibration hardware so that they can be calibrated simultaneously. 4. start self-calibration by setting bit 4 (calen) in register 0x12. wait approximately 300 calibration clock cycles. 5. check if the self-calibration has completed by reading bit 6 (calstati) and bit 7 (calstatq) in register 0x0f. logic 1 indicates that the calibration has completed. 6. when the self-calibration has completed, write 0x00 to register 0x12. 7. disable the calibration clock by clearing bit 3 (calclk) in register 0x0e.
ad9114/ad9115/ad9116/ad9117 rev. a | page 45 of 80 the ad9114/ad9115/ad9116/ad9117 allow reading and writing of the calibration coefficients. there are 32 coefficients in total. the read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several self-calibration cycles and loading the averaged results back into the device. to read the calibration coefficients, use the following steps: 1. select which dac core to read by setting either bit 4 (calseli) for the i dac or bit 5 (calselq) for the q dac in register 0x0e. write the address of the first coefficient (0x01) to register 0x10. 2. set bit 2 (smemrd) in register 0x12 by writing 0x04 to register 0x12. 3. read the 6-bit value of the first coefficient by reading the contents of register 0x11. 4. clear the smemrd bit by writing 0x00 to register 0x12. 5. repeat step 2 through step 4 for each of the remaining 31 coefficients by incrementing the address by 1 for each read. 6. deselect the dac core by clearing either bit 4 (calseli) for the i dac and/or bit 5 (calselq) for the q dac in register 0x0e. to write the calibration coefficients to the device, use the following steps: 1. select which dac core to write to by setting either bit 4 (calseli) for the i dac or bit 5 (calselq) for the q dac in register 0x0e. 2. set bit 3 (smemwr) in register 0x12 by writing 0x08 to register 0x12. 3. write the address of the first coefficient (0x01) to register 0x10. 4. write the value of the first coefficient to register 0x11. 5. repeat step 2 through step 4 for each of the remaining 31 coefficients by incrementing the address by one for each write. 6. clear the smemwr bit by writing 0x00 to register 0x12. 7. deselect the dac core by clearing either bit 4 (calseli) for the i dac or bit 5 (calselq) for the q dac in register 0x0e. coarse gain adjustment option 1 a coarse full-scale output current adjustment can be achieved using the lower six bits in register 0x0d. this adds or subtracts up to 20% from the band gap voltage on pin 34 (refio), and the voltage on the fsadjx resistors tracks this change. as a result, the dac full-scale current varies by the same amount. a secondary effect to changing the refio voltage is that the full-scale voltage in the auxdac also changes by the same magnitude. the register uses twos complement format, in which 011111 maximizes the voltage on the refio node and 100000 minimizes the voltage. 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0 8 16 24 32 40 48 56 code v ref (v) 07466-058 figure 97. typical v ref voltage vs. code option 2 while using the internal fsadjx resistors, each main dac can achieve independently controlled coarse gain using the lower six bits of register 0x04 (irset[5:0 ]) and register 0x07 (qrset[5:0]). unlike coarse gain option 1, this impacts only the main dac full-scale output current. the register uses twos complement format and allows the output current to be changed in approximately 0.25 db steps. 20 18 22 16 10 12 14 8 6 4 2 0 102030405060 xr set code i f (ma) v out_q or v out_i 07466-059 figure 98. effect of xr set code option 3 even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the fsadjx pins. any noise injected here appears as amplitude modulation of the output. thus, a portion of the required series resistance (at least 20 k) must be installed right at the pin. a range of 10% is quite practical using this method. option 4 as in option 3, when the device is in pin mode, both full-scale values can be adjusted by sourcing or sinking current from the refio pin. noise injected here appears as amplitude modulation of the output; therefore, a portion of the required series resistance (at least 10 k) must be installed at the pin. a range of 25% is quite practical when using this method.
ad9114/ad9115/ad9116/ad9117 rev. a | page 46 of 80 fine gain using the internal common-mode resistor each main dac has independent fine gain control using the lower six bits in register 0x03 (i dacgain[5:0]) and register 0x06 (q dacgain[5:0]). unlike coarse gain option 1, this impacts only the main dac full-scale output current. these registers use straight binary format. one application in which straight binary format is critical is for side-band suppression while using a quadrature modulator. this is described in more detail in the applications information section. these devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the dac outputs. by default, the common-mode resistor is not connected. when enabled, it can be adjusted from ~60 to ~260 . each main dac has an independent adjustment using the lower six bits in register 0x05 (ircml[5:0]) and register 0x08 (qrcml[5:0]). 260 220 240 200 180 160 140 120 100 80 60 0 8 16 24 32 40 48 56 code resistance ( ? ) 07466-062 11.10 11.00 10.90 10.80 10.70 10.60 10.50 0 8 16 24 32 40 48 56 64 gain dac code i outfs (ma) 3.3v dac1 3.3v dac2 1.8v dac1 1.8v dac2 0 7466-060 figure 101. typical cml resistor value vs. register code using the cmlx pins for optimal performance figure pical dc gain characteristics the cmlx pins also serve to change the dac bias voltages in the parts allowing them to run at higher dc output bias voltages. when running the bias voltage below 0.9 v and an avdd of 3.3 v, the parts perform optimally when the cmlx pins are tied to ground. when the dc bias increases above 0.9 v, set the cmlx pins at 0.5 v for optimal performance. the maximum dc bias on the dac output should be kept at or below 1.2 v when the supply is 3.3 v. when the supply is 1.8 v, keep the dc bias close to 0 v and connect the cmlx pins directly to ground. using the internal termination resistors the ad9117/ad9116/ad9115/ad9114 have four 62.5 termination internal resistors (two for each dac output). to use these resistors to convert the dac output current to a voltage, connect each dac output pin to the adjacent load pin. for example, on the i dac, ioutp must be shorted to rlip and ioutn must be shorted to rlin. in addition, the cmli or cmlq pin must be connected to ground directly or through a resistor. if the output current is at the nominal 20 ma and the cmli or cmlq pin is tied directly to ground, this produces a dc common-mode bias voltage on the dac output equal to 0.5 v. if the dac dc bias must be higher than 0.5 v, an external resistor can be connected between the cmli or cmlq pin and ground. this part also has an internal common-mode resistor that can be enabled. this is explained in the using the internal common-mode resistor section. i dac or q dac xr cm cml rlin ioutn ioutp rlip 62.5 ? 62.5 ? figure 100. simplified internal load options
ad9114/ad9115/ad9116/ad9117 rev. a | page 47 of 80 applications information output configurations the following sections illustrate some typical output configu- rations for the ad9114/ad9115/ad9116/ad9117. unless otherwise noted, it is assumed that i xoutfs is set to a nominal 20 ma. for applications requiring the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration can consist of either an rf transformer or a differential op amp configuration. the trans- former configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or a low output impedance. a single-ended output is suitable for applications in which low cost and low power consumption are primary concerns. differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion, as shown in figure 102 . the distortion performance of a transformer typically exceeds that available from standard op amps, particularly at higher frequencies. transformer coupling provides excellent rejection of common-mode distortion (that is, even-order harmonics) over a wide frequency range. it also provides electrical isolation and can deliver voltage gain without adding noise. transformers with different impedance ratios can also be used for impedance matching purposes. the main disadvantages of transformer coupling are low frequency roll-off, lack of power gain, and high output impedance. ad9114/ad9115/ ad9116/ad9117 ioutn ioutp 29 28 optional r diff r load 07466-063 figure 102. differential output using a transformer the center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on ioutp and ioutn within the output common-mode voltage range of the device. note that the dc component of the dac output current is equal to i ioutfs and flows out of both ioutp and ioutn. the center tap of the transformer should provide a path for this dc current. in most applications, agnd provides the most convenient voltage for the transformer center tap. the comple- mentary voltages appearing at ioutp and ioutn (that is, v ioutp and v ioutn ) swing symmetrically around agnd and should be maintained with the specified output compliance range of the ad9114/ad9115/ad9116/ad9117. a differential resistor, r diff , can be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff , as reflected by the transformer, is chosen to provide a source termination that results in a low voltage standing wave ratio (vswr). note that approximately half the signal power is dissipated across r diff . single-ended buffered output using an op amp an op amp, such as the ada4899-1 , can be used to perform a single- ended current-to-voltage conversion, as shown in figure 103 . the ad9114/ad9115/ad9116/ad9117 are configured with a pair of series resistors, r s , off each output. for best distortion performance, r s should be set to 0 . the feedback resistor, r fb , determines the peak-to-peak signal swing by the formula v out = r fb i fs the common-mode voltage of the output is determined by the formula 2 1 fs fb b fb ref cm ir r r vv ? ? ? ? ? ? ? ? ? += the maximum and minimum voltages out of the amplifier are, respectively, ? ? ? ? ? ? ? ? += b fb ref max r r vv 1 v min = v max ? i fs r fb +5v ad9114/ad9115/ ad9116/ad9117 ioutp ioutn 29 r fb v out refio 34 28 r s avss 25 c f c r s r b + ? ada4899-1 ?5v 07466-064 figure 103. single-suppl y, single-ended buffer
ad9114/ad9115/ad9116/ad9117 rev. a | page 48 of 80 differential buffered output using an op amp a dual op amp (see the circuit shown in figure 104 ) can be used in a differential version of the single-ended buffer shown in figure 103 . the same rc network is used to form a one-pole differential, low-pass filter to isolate the op amp inputs from the high frequency images produced by the dac outputs. the feed- back resistors, r fb , determine the differential peak-to-peak signal swing by the formula v out = 2 r fb i fs the maximum and minimum single-ended voltages out of the amplifier are, respectively, ? ? ? ? ? ? ? ? += b fb ref max r r vv 1 v min = v max ? r fb i fs the common-mode voltage of the differential output is determined by the formula v cm = v max ? r fb i fs ad9114/ad9115/ ad9116/ad9117 ioutp ioutn r fb v out refio 34 28 r s avss 25 c f c r fb r b c f r s r b 29 ada4841-2 ada4841-2 07466-065 figure 104. single-supply differential buffer auxiliary dacs the dacs of the ad9114/ad9115/ad9116/ad9117 feature two versatile and independent 10-bit auxiliary dacs suitable for dc offset correction and similar tasks. because the auxdacs are driven through the spi port, they should never be used in timing-critical applications, such as inside analog feedback loops. to keep the pin count reasonable, these auxiliary dacs each share a pin with the corresponding fsadjx resistor. they are, therefore, usable only when enabled and when that dac is operated on its internal full-scale resistors. a simple i-to-v converter is implemented on-chip with selectable shunt resistors (3.2 k to 16 k) such that if refio is set to exactly 1 v, refio/2 equals 0.5 v and the following equation describes the no load output voltage: k 16 5.1 v5.0 ? ? ? ? ? ? ? ? ??= figure 105 illustrates the function of all the spi bits controlling these dacs with the exception of the qauxen (register 0x0a) and iauxen (register 0x0c) bits and gating to prohibit r s < 3.2 k. op amp auxdac [9:0] a v dd rng0 rng1 refio 2 16k 16k 16k 4k 8k ofs2 ofs1 ofs0 (ofs > 4 = 4) aux pin rng: 00 = 125a f s 01 = 62a f s 10 = 31a f s 11 = 16a f s 07466-066 figure 105. auxdac simplified circuit diagram the spi speed limits the update rate of the auxiliary dacs. the data is inverted such that i auxdac is full scale at 0x000 and zero at 0x1ff, as shown in figure 106 . 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 100 120 130 dac current (a) output (v) 110 r offset = 3.3k r offset = 4k r offset = 5.3k r offset = 8k r offset = 16k op amp output voltage vs. changes in r offset and dac current in a 0 7466-067 figure 106. auxdac op amp output vs. current, avdd = 3.3 v no load, auxdac 0x1ff to 0x000
ad9114/ad9115/ad9116/ad9117 rev. a | page 49 of 80 two registers are assigned to each dac with 10 bits for the actual dac current to be generated, a 3-bit offset (and gain) adjustment, a 2-bit current range adjustment, and an enable/ disable bit. setting the qauxofs (register 0x0a) and iauxofs (register 0x0c) bits to all 1s disables the respective op amp and routes the dac current directly to the respective fsadji/auxi or fsadjq/auxq pins. this is especially useful when the loads to be driven are beyond the limited capability of the on-chip amplifier. when not enabled (qauxen or iauxen = 0), the respective dac output is in open circuit. dac-to-modulator interfacing the auxiliary dacs can be used for local oscillator (lo) cancellation when the dac output is followed by a quadrature modulator. this lo feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the dac output offset voltage mismatch) and can degrade system performance. typical dac-to-quadrature modulator interfaces are shown in figure 107 and figure 108 , with the series resistor value chosen to give an appropriate adjustment range. figure 107 also shows external load resistors in use. often, the input common- mode voltage for the modulator is much higher than the output compliance range of the dac, so that ac coupling or a dc level shift is necessary. if the required common-mode input voltage on the quadrature modulator matches that of the dac, the dc blocking capacitors in figure 107 can be removed and the on-chip resistors can be connected. ad9114/ad9115/ ad9116/ad9117 auxdac1 ad9114/ad9115/ ad9116/ad9117 i dac 5k? to 100k ? 50? 50? optional passive filtering modulator v+ quadrature modulator i or q inputs 0.1f 0.1f 07466-268 figure 107. typical use of auxiliary dacs figure 108 shows a greatly simplified circuit that takes full advantage of the internal components supplied in the dac. a low-pass or band-pass passive filter is recommended when spurious signals from the dac (distortion and dac images) at the quadrature modulator inputs can affect the system performance. in the example shown in figure 108 , the filter must be able to pass dc to properly bias the modulator. placing the filter at the location shown in figure 107 and figure 108 allows easy design of the filter, because the source and load impedances can easily be designed close to 50 for a 20 ma full-scale output. when the resistance at the modulator inputs is known, an optimum value for the series resistor can be calculated from the modulator input offset voltage ratings. ad9114/ad9115/ ad9116/ad9117 auxdac ad9114/ad9115/ ad9116/ad9117 i or q dac 5k? 50 ? 50 ? 100 ? optional low- pass filtering adl5370 family i or q inputs 07466-269 figure 108. typical use of auxiliary dacs when dc coupling to quadrature modulator adl537x family correcting for nonideal performance of quadrature modulators on the if-to-rf conversion analog quadrature modulators make it very easy to realize single sideband radios. these dacs are most often used to make radio transmitters, such as in cell phone towers. however, there are several nonideal aspects of quadrature modulator performance. among these analog degradations are gain mismatch and lo feedthrough. gain mismatch the gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. this leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect. lo feedthrough the quadrature modulator has a finite dc referred offset, as well as coupling from its lo port to the signal inputs. these can lead to a significant spectral spur at the frequency of the quadrature modulator lo. the ad9114/ad9115/ad9116/ad9117 have the capability to correct for both of these analog degradations. however, understand that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting them may be necessary. i/q channel gain matching fine gain matching is achieved by adjusting the values in the dac fine gain adjustment registers. for the i dac, these values are in the i dac gain register (register 0x03, i dacgain[5:0]). for the q dac, these values are in the q dac gain register (register 0x06, q dacgain[5:0]). these are 6-bit values that cover 2% of full scale. to perform gain compensation by starting from the default values of zero, raise the value of one of these registers a few steps until it can be determined if the amplitude of the unwanted image is increased or decreased. if the unwanted image increases in amplitude, remove the step and try the same adjustment on the other dac control register. iterate register changes until the rejection cannot be improved further. if the fine gain adjustment range is not sufficient to find a null (that is, the register goes full scale with no null apparent), adjust the course gain settings of the two dacs accordingly and try again. variations on this simple method are possible.
ad9114/ad9115/ad9116/ad9117 rev. a | page 50 of 80 note that lo feedthrough compensation is independent of phase compensation. however, gain compensation can affect the lo compensation because the gain compensation may change the common-mode level of the signal. the dc offset of some modulators is common-mode level dependent. therefore, it is recommended that the gain adjustment be performed prior to lo compensation. lo feedthrough compensation to achieve lo feedthrough compensation in a circuit, each output of the two auxdacs must be connected through a 10 k resistor to one side of the differential dac output. see the auxiliary dacs section for details of how to use auxdacs. the purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, thereby adding a slight dc bias to one or the other of the quadrature modulator signal inputs. to achieve lo feedthrough compensation, the user should start with the default conditions of the auxdac registers and then increment the magnitude of one or the other auxdac output voltages. while this is being done, the amplitude of the lo feedthrough at the quadrature modulator output should be sensed. if the lo feedthrough amplitude increases, try either decreasing the output voltage of the auxdac being adjusted or try adjusting the output voltage of the other auxdac. it may take practice before an effective algorithm is achieved. the ad9114/ad9115/ad9116/ ad9117 evaluation board can be used to adjust the lo feedthrough down to the noise floor, although this is not stable over temperature. results of gain and offset correction the results of gain and offset correction can be seen in figure 109 and figure 110 . figure 109 shows the output spectrum of the quadrature demodulator before gain and offset correction. figure 110 shows the output spectrum after correction. the lo feedthrough spur at 450 mhz has been suppressed to the noise level. this result can be achieved by applying the correction, but the correction must be repeated after a large change in temperature. note that gain matching improves the negative frequency image rejection, but it is also related to the phase mismatch in the quadrature modulator. it can be improved by adjusting the relative phase between the two quadrature signals at the digital side or properly designing the low-pass filter between the dacs and quadrature modulators. phase mismatch is frequency dependent; therefore, routines must be developed to adjust it if wideband signals are desired. 5 ?5 ?15 ?25 ?35 ?45 ?55 ?65 ?75 ?85 ?95 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 447.5 449.0 450.0 451.0 452.5 frequency (mhz) db 07466-070 figure 109. ad9114/ad9115/ad9116/ad 9117 and adl5370 with a single- tone signal at 450 mhz, no gain or lo compensation 5 ?5 ?15 ?25 ?35 ?45 ?55 ?65 ?75 ?85 ?95 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 447.5 449.0 450.0 451.0 452.5 frequency (mhz) db 07466-071 figure 110. ad9114/ad9115/ad9116/ad 9117 and adl5370 with a single- tone signal at 450 mhz, gain and lo compensation optimized
ad9114/ad9115/ad9116/ad9117 rev. a | page 51 of 80 modifying the evaluation board to use the adl5370 on-board quadrature modulator t he evaluation board contains an analog devices, inc., adl5370 quadrature modulator. the ad9114/ad9115/ ad9116/ad9117 and the adl5370 provide an easy-to-interface dac/modulator combination that can be easily characterized on the evaluation board. solderable jumpers can be configured to evaluate the single-ended or differential outputs of the ad9114/ ad9115/ad9116/ad9117. this setup is the default configuration from the factory and consists of the following population of the components: ? jp55, jp56, jp76, jp82unsoldered ? r13, r14, r52, r53unpopulated ? r50, r57, t1, t2populated t o e v a lu ate t he adl5370 on this board, the population of these same components should be reversed so that they are in the following positions: ? jp55, jp56, jp76, jp82soldered ? r13, r14, r52, r53populated ? r50, r57, t1, t2unpopulated the auxdac outputs can be connected to test point tp44 and test point tp45 if lo feedthrough compensation is necessary.
ad9114/ad9115/ad9116/ad9117 rev. a | page 52 of 80 evaluation board schematics and artwork schematics 07466-184 5v fb gnd in3 nc out5 sd adp3334 in4 out6 5v 5v cc0603 cc0603 cc0603 rc0603 rc0603 rc0603 b a b a b a ba cc0603 cc0603 acase cc0603 acase 5v 5v 5v 5v 5v rc0603 rc0603 5v 5v 5v 5v 5v 5v rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 5v 5v 5v 5v 5v 5v 5v 5v adp3334 adp3334 b a gnd in4 sd adp3334 in3 gnd in4 sd in3 fb gnd in4 nc out5 sd in3 out6 cc0603 cc0603 acase cc0603 acase cc0603 ba cc0603 acase cc0603 cc0603 fb gnd in3 nc out5 sd adp3334 in4 out6 fb nc out5 out6 fb nc out5 out6 ba smaedge 5v smaedge smaedge smaedge smaedge c c 5v lc1812 lc1812 lc1812 lc1812 lc1812 lc1812 lc1812 lc1812 lc1812 5v 5v 5v 5v lc1812 ba rc0603 rc0603 ba 5v rc0603 ba 1.8 3.3 1.8 3.3 1.8 3.3 1.8 3.3 3.3 1.8 2 3 1 jp88 64.9k r32 r92 64.9k 78.7k r4 13 2 jp89 r3 78.7k 78.7k r29 13 2 jp29 dvddx_in cvddx_in avdd_in dvdd_in cvdd_in l3 exc-cl4532u1 exc-cl4532u1 l16 l19 exc-cl4532u1 blk tp23 tp24 red cvddx_in cvddx l4 exc-cl4532u1 exc-cl4532u1 l12 red tp8 tp9 blk dvddx_in dvddx exc-cl4532u1 l7 tp6 blk red tp5 avdd_in avdd l1 exc-cl4532u1 exc-cl4532u1 l5 exc-cl4532u1 l6 blk tp4 tp13 red dvdd_in blk tp14 red tp12 c10 0.1uf dvdd cvdd cvdd_in 2 1 5vgnd;3,4,5 j8 1 2 j5 5vgnd;3,4,5 1 2 5vgnd;3,4,5 j2 2 1 j4 5vgnd;3,4,5 31 2 jp6 8 7 5 1 2 3 4 6 u2 c2 6.3v 10uf c7 0.1uf 0.1uf c3 13 2 jp22 c8 0.1uf 0.1uf c6 0.1uf c9 10uf 6.3v c4 c5 6.3v 10uf c16 0.1uf 0.1uf 0.1uf 0.1uf c15 c1 6.3v 10uf l2 exc-cl4532u1 6 4 3 2 1 5 7 8 u4 2 3 1 jp26 8 7 5 1 2 3 4 6 u6 6 4 3 2 1 5 7 8 u7 c14 1uf 1uf c17 c20 1uf 1uf c31 c37 1uf 1uf c21 c18 1uf 1uf c12 c38 100pf 100pf c30 c19 100pf 100pf c13 r36 76.8k 76.8k r31 r23 76.8k 76.8k r2 r30 64.9k 64.9k r12 r8 64.9k r10 78.7k 78.7k r5 10uf 6.3v c57 c61 c60 2 1 3 jp10 31 2 jp54 2 1 3 jp15 31 2 jp78 76.8k r25 100pf c89 1uf c88 c86 1uf 8 7 5 1 2 3 4 6 u11 1 2 j11 5vgnd;3,4,5 smaedge 5v 5vint 5vin jp3 5vusb 1 2 j3 5vgnd;3,4,5 jp28 figure 111. power supplies and filters
ad9114/ad9115/ad9116/ad9117 rev. a | page 53 of 80 rnetcts743-8 rc0402 rnetcts743-8 2 22 22 rnetcts743-8 rnetcts743-8 of u1. s5 to pin 18 no stub match length to path from 10 11 12 13 14 15 2 3 4 5 6 7 8 1 16 9 dnp rp1 10 11 12 13 14 15 2 3 4 5 6 7 8 1 16 9 dnp rp5 db13 db12 db11 db9 db8 db7 db0x db1x db2x db3x db4x db5x db6x db6 10 11 12 13 14 15 2 3 4 5 6 7 8 116 9 rp3 1 r6 0 msb tp22 tp10 blk wht db13x db7x db8x db9x db10x db11x db12x db10 db5 db4 db3 db2 db1 db0 9 16 1 8 7 6 5 4 3 215 14 13 12 11 10 rp4 ssw-120-02-sm-d-r- a header right angle female pcb bottom side 1 3 7 5 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 j1 1 db13x db12x db11x db10x db9x db8x db7x db6x db5x db4x db3x db2x db1x 07466-185 digital inputs 1 in j1 and rp3, the msb is db13, db11, db9, or db7, depending on the part. figure 112. digital inputs
ad9114/ad9115/ad9116/ad9117 rev. a | page 54 of 80 07466-186 rc0402 rc0402 rc0402 rc0402 c c c cc rc0402 rc0402 rc0402 cc0603 cc0603 rc0603 rc0402 sn74lvc1g34dck cc0603 cc0603 cc0603 cc0603 cc0603 cc0402 cc0402 cc0603 acase rc0402 cc0402 cc0402 c rc0402 gnd out en ovcc 40-lead lfcsp ad9717 the ad9114/ad9115/ad9116/ad9117 can be used in u1. db10 db9 db8 dvddio dvss dvdd db7 db6 db5 db4 db3 db2 db1 db0 (lsb) dclkio cvdd clkin cvss cmlq db12 db13 (msb) cs/pwrdn sclk/clkmd reset/pinmd refio fsadji/auxi fsadjq/auxq cmli rlin ioutn ioutp rlip avdd avss rlqp qoutp rlqn db11 qoutn sdio/format rc0402 cc0402 cc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 c = share component pad. keep parallel wht tp25 iotc qotc dnp r80 cvdd clkin dclkio r17 dnp dvddx 49.9 r18 10k r71 tp26 wht c34 00.1uf wht tp30 cvddx avdd refio r65 dclkio clkin r33 1 3 42 sw1 dgnd;5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 36 35 34 33 32 31 30 29 28 27 26 25 24 23 21 1 22 37 u1 agnd;41 1 23 4 u12 osc-s1703 r110 dnp dnp r69 dgnd;3,4,5 s11 out2r 00 0 0 out0r 00.1uf c77 c78 00.01uf r107 dnp 10k r108 1nf c56 c55 00.1uf tp3 wht 1uf c39 jp11 jp32 jp33 jp34 jp35 4.7uf 6.3v c59 0.1uf c11 0.01uf 32c 82c 0.01uf 24 u8 dvddx;5 dgnd;3 r70 10k dnp r68 cgnd;3,4,5 s5 r34 0 dnp dvdd avdd c24 0.1uf cvdd r7 10k 0.01uf c25 0.1uf c26 0.1uf c27 r64 dnp r66 r67 0 r72 00.1uf c101 mode-sdio db11 fsadj2 fsadj1 rmode-sclk sleep-csb db13 db12 db0 (lsb) db1 db2 db3 db4 db5 db6 db7 dvddio db8 db9 db10 ioutb iouta qouta qoutb dvdd r122 dvddx r19 r20 0 dnp r21 0 dnp r26 iotc qotc iot_cml qot_cml rc0402 c rc0402 rc0402 r47 0 0 r46 0 r48 figure 113. clock input and dut
ad9114/ad9115/ad9116/ad9117 rev. a | page 55 of 80 07466-187 rc0603 rc0603 rc0603 cc0402 acase dnp rc0805 rc0805 rc0805 rc0603 rc0603 rc0603 rc0603 adtl1-12 ps adt9-1t sp rc0603 rc0603 acase cc0603 cc0805 cc0603 cc0603 cc0603 cc0603 rc0402 rc0402 rc0402 rc0402 rc0402 +in +v -in dis fb -v2 -v1 out rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 fsadj resistors must have low tc iout network and fsadj1 wht tp31 r14 dnp when r13 and r14 are not dnp, 499 is recommended when c95 is not dnp, 10pf to 1nf is recommended r13 dnp iouta ioutb jp90 fsadj1 0 r79 r123 0-dnp dnp r37 s3 r9 dnp r11 0 agnd;3,4,5 agnd;3,4,5 agnd;3,4,5 agnd;3,4,5 r94 0 10-dnp r111 0 r93 s4 1 7 4 5 3 2 6 8 ada4899-1 u13 agnd;9 dnp c105 1uf ceramic r116 0 499 r115 0 r117 refio opampin c107 0.1uf c106 0.1uf 0.1uf c108 p5v p5v n5v c103 10v 10uf org tp40 tp39 red tp41 blk 0.1uf c22 opampin r57 453 2 5 3 1 6 4 t8 1 34 6 t2 wht tp34 r99 100k d1n d1p c95 dnp tp1 wht dnp r98 r97 dnp jp7 0.1% 32k r1 dnp tp33 r22 dnp r51 8k 0.1% r49 16k 0.1% jp9 jp8 s9 dnp tp32 dnp jp12 10uf 10v c104 n5v r113 499 c102 0.2nf 15 r114 r118 dnp dnp r119 jp55 jp56 100k r35 tp44 wht 1 2 s12 0-dnp r15 iot_cml era6yeb323v, era6y era6yeb323v, era6y era6yeb323v, era6y figure 114. iout network and fsadj1
ad9114/ad9115/ad9116/ad9117 rev. a | page 56 of 80 07466-188 rc0603 rc0603 rc0603 rc0603 rc0603 cc0603 adt9-1t sp adtl1-12 p s rc0805 rc0805 era6yeb323v, era6y era6yeb323v, era6y era6yeb323v, era6y rc0603 rc0603 rc0603 rc0805 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 cc0603 fsadj resistors must have low tc qout network and fsadj2 r54 dnp tp17 wht fsadj2 jp91 jp82 wht tp38 r53 dnp r52 dnp qouta qoutb d2n dnp r56 r42 dnp 0 r83 0 r124 0 s8 r38 0 r106 0 0 r105 opampin dnp r112 r50 453 r59 16k 0.1% r60 8k 0.1% d2p tp37 dnp dnp r101 0.1uf c48 s6 jp21 jp20 jp16 0.1% 32k r58 16 34 t1 s10 dnp 1 2 agnd;3,4,5 agnd;3,4,5 agnd;3,4,5 1 2 3 4 5 6 t5 wht tp35 r102 100k c96 when c96 is not dnp, 10pf to 1nf is recommended dnp r100 dnp jp77 dnp tp36 r120 dnp dnp r121 jp76 100k r55 tp45 wht r16 qot_cml when r52 and r53 are not dnp, 499 is recommended when r112 is not dnp, 10 is recommended figure 115. qout network and fsadj2
ad9114/ad9115/ad9116/ad9117 rev. a | page 57 of 80 5v 5v 5v 5v 5v rc0402 rc0402 cc0603 cc0603 rc0402 rc1206 cc0603 cc0603 cc0603 cc0603 mlx-0532610571 cc0603 cc0603 rc0603 cc0603 grn cc0603 rc0402 rc0402 cc0603 cc0603 rc0402 rc0402 2 vbus d- d+ id-x gnd-4 avdd1 avdd2 avss mclr-vpp-re3 osc1-clk1 n31c osc2-clko-ra6 ra0-an0 ra1-an1 ra2-an2-vref- ra3-an3-vref+ ra5-an4-hlvdin ra4-t0cki-rcv rb0-an12-int0 rb1-an10-int1 rb2-an8-int2-vmo rb3-an9-vpo rb4-an11-kbi0 rb5-kbi1-pgm rb6-kbi2-pgc rb7-kbi3-pgd rc0-tioso-t1cki rc1-t1osi-uoe rc2-ccp1 rc4-d--vm rc5-d+-vp rc6-tx-ck rc7-rx-dt rd0 rd1 rd2 rd3 rd4 rd5 rd6 rd7 re0-an5 re1-an6 re2-an7 vdd1 vdd2 vss1 vss2 vusb pic18f4450 a1 a2 a3 a4 en gnd nca vcca vccy y1 y2 y3 y4 adg3304 a1 a2 a3 a4 en gnd nca vcca ncy vccy y1 y2 y3 y4 adg3304 pcb bottom side pcb top side 2 3 4 5 8 7 1 14 13 12 11 10 6 9 u5 10 11 12 13 14 1 9 8 6 7 5 4 3 2 u14 7 28 30 18 32 13 33 19 20 21 23 22 24 9 10 11 12 14 15 16 17 34 35 36 42 43 44 1 38 39 40 41 2 3 4 5 25 26 27 8 29 6 31 37 u3 5vgnd;45 r28 s1 s3 1 2 3 4 5 p1 r43 0 mosi miso 22 r103 mosi miso csb en2 l15 exc-cl3225u1 wht tp20 wht tp18 tp2 dnp r44 22 sclk 3 y1 20.000mhz 5vgnd;2 5vusb 5vusb 0.1uf c114 c100 0.1uf 0r82 r62 0 mode-sdio r87 0 dvdd ssel2 10pf-1% c49 r63 rc0403 499 2 1 d1 lnj312g8tra r27 1m 5vusb 0.1uf c109 5vusb c32 6.3v 10uf c33 10pf-1% 470nf c110 2 3 4 5 1 mp1 mp2 p3 mosi en1 en2 sck ssel1 5vusb c84 0.1uf 0.1uf c97 c98 0.1uf 0.1uf c99 miso mosi sck ssel1 ssel2 sck miso c112 0.1uf 0.1uf c111 5vusb r39 22 22 r40 r41 22 22 rmode-sclk 22 r45 ra0 mode-sdo 5vusb blk tp7 tp19 wht dvddx en1 sleep-csb sdio 07466-189 figure 116. spi port
ad9114/ad9115/ad9116/ad9117 rev. a | page 58 of 80 07466-190 cc0402 cc0402 acase cc0402 cc0402 etc1-1-13 sp cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 acase acase acase cc0402 rc0603 rc0603 rc0603 smaedge agnd;3,4,5 smaedge agnd;3,4,5 cc0805 cc0805 cc0805 cc0805 lc1008 adtl1-12 nc=2,5 ps ps nc=2,5 rc0603 vps1b vps1c vps1d com2a loip loin com2b com3a com3b vout vps2a vps2b vps3 vps4 vps5 ibbp ibbn com4a qbbn qbbp vps1a com1a com1b com4b adtl1-12 rc0603 rc0603 cc0402 cc0402 vddm 100pf c87 c53 100pf 100pf c54 r73 r74 6 4 3 1 t6 0 0 0 0 mod_in mod_ip 4 5 6 7 8 9 10 11 31 12 14 15 16 17 18 19 20 21 23 24 3 1 2 22 u9 agnd;25 adl5370 r78 r75 1 34 6 t3 l17 dnp lc1008 red tp42 blk tp21 tp16 red vddm dnp l14 vddm_in c91 dnp c79 7.5pf cc0805 c80 4.7pf cc0805 c81 4.7pf c92 dnp c82 lc1008 l10 lc1008 1.8uh 1.8uh l11 7.5pf 1 2 j7 1 2 j6 1k 1k r24 r61 0.1uf c90 c83 100pf c63 100pf 0.1uf c72 10v 10uf c41 c44 10uf 10v c52 0.1uf 0.1uf c47 c50 100pf 10v 10uf c43 1 2 34 5 t4 c73 100pf 100pf c51 0.1uf c36 22uf 16v c35 exc-cl4532u1 l13 lc1812 c29 0.1uf tp43 blk mod_qp mod_qn mod_in mod_ip vddm modulated output vddm vddm d1p d1n cc0805 cc0805 cc0805 cc0805 lc1008 l20 dnp lc1008 dnp l18 c93 dnp c64 7.5pf cc0805 c65 4.7pf cc0805 c74 4.7pf c94 dnp c75 lc1008 l8 lc1008 1.8uh 1.8uh l9 7.5pf d2p d2n mod_qp mod_qn figure 117. modulated output
ad9114/ad9115/ad9116/ad9117 rev. a | page 59 of 80 cc0402 cc0402 cc0402 cc0402 c113 0.1u f 0.1uf c85 c58 0.1u f 0.1uf c40 c c c c c c c c c cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 jtx-4-10t+ sp hsms-281c rc0805 cc0402 cc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 cc0402 1:4 c42 0.1uf 1nf c62 out0r r88 r89 dnp r90 when r90 and r109 are not dnp, 49.9 is recommended cvddx 4.12k r81 13 4 2 sw2 cgnd;5 cvddx 0.1uf c46 c45 0.1uf r91 49.9 12 3 d3 t9 0.1uf c66 c67 0.1uf 0.1uf c68 c76 0.1uf 0.1uf c71 c70 0.1uf 0.1uf c69 out2r r109 dnp j 10 07466-191 rc0402 0r86 ra0 c c ad9512bcpz dsyncb vs1 vs2 nc1 vs3 clk2 clk2b vs4 clk1 clk1b func status sclk sdio sdo csb vs5 gnd1 out2b out2 vs6 vs7 vs18 vs17 gnd6 rset vs16 gnd5 out0 out0b vs15 vs14 gnd4 gnd3 vs13 out3 out3b vs12 vs11 out4 out4b vs10 vs9 out1 out1b vs8 gnd2 dsync mode-sdio mode-sdo 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 52 42 1 u10 cgnd;49 cvddx cvddx cvddx cvddx cvddx cvddx rmode-sclk sleep-csb cvddx cvddx cvddx cvddx cvddx cvddx cvddx cvddx cvddx cvddx cvddx cvddx 0 0 r76 1.8k 1.8k r77 2 3 1 5 6 4 clock driver chip cgnd;3,4,5 figure 118. cloc k driver chip
ad9114/ad9115/ad9116/ad9117 rev. a | page 60 of 80 silkscreens 07466-203 figure 119. layer 2, ground plane
ad9114/ad9115/ad9116/ad9117 rev. a | page 61 of 80 07466-204 figure 120. layer 3, power plane
ad9114/ad9115/ad9116/ad9117 rev. a | page 62 of 80 07466-205 figure 121. assemblyprimary side
ad9114/ad9115/ad9116/ad9117 rev. a | page 63 of 80 07466-206 figure 122. assemblysecondary side
ad9114/ad9115/ad9116/ad9117 rev. a | page 64 of 80 07466-217 figure 123. solder maskp rimary side with socket
ad9114/ad9115/ad9116/ad9117 rev. a | page 65 of 80 07466-207 figure 124. solder masksecondary side
ad9114/ad9115/ad9116/ad9117 rev. a | page 66 of 80 07466-208 figure 125. hard gold plated with bumps and socket
ad9114/ad9115/ad9116/ad9117 rev. a | page 67 of 80 0 7466-209 figure 126. primary side paste
ad9114/ad9115/ad9116/ad9117 rev. a | page 68 of 80 07466-210 figure 127. secondary side paste
ad9114/ad9115/ad9116/ad9117 rev. a | page 69 of 80 07466-211 figure 128. silkscreenprimary side
ad9114/ad9115/ad9116/ad9117 rev. a | page 70 of 80 07466-212 figure 129. silkscreensecondary side
ad9114/ad9115/ad9116/ad9117 rev. a | page 71 of 80 07466-213 figure 130. layer 1primary side
ad9114/ad9115/ad9116/ad9117 rev. a | page 72 of 80 07466-214 figure 131. layer 4secondary side
ad9114/ad9115/ad9116/ad9117 rev. a | page 73 of 80 07466-215 figure 132. immersion gold, no socket, no bumps
ad9114/ad9115/ad9116/ad9117 rev. a | page 74 of 80 07466-216 figure 133. solder maskprimary side, no socket
ad9114/ad9115/ad9116/ad9117 rev. a | page 75 of 80 bill of materials table 18. qty reference designator device package description part no./ manufacturer 6 c1, c2, c4, c5, c32, c57 capsmda acase 10 f, 6.3 v capacitor 17 c3, c6, c7, c8, c9, c10, c11, c15, c16, c22, c24, c26, c27, c48, c60, c61, c107 cc0603 cc0603 0.1 f capacitor 11 c12, c14, c17, c18, c20, c21, c31, c37, c39, c86, c88 cc0603 cc0603 1 f capacitor 5 c13, c19, c30, c38, c89 cc0603 cc0603 100 pf capacitor 3 c23, c25, c28 cc0603 cc0603 0.01 f capacitor 6 c29, c36, c47, c52, c72, c90 cc0402 cc0402 0.1 f capacitor 2 c33, c49 cc0603 cc0603 10 pf, 1% capacitor 18 c34, c40, c42, c45, c46, c55, c58, c66, c67, c68, c69, c70, c71, c76, c77, c85, c101, c113 cc0402 cc0402 0.1 f capacitor 1 c35 capsmda acase 22 f,16 v capacitor 3 c41, c43, c44 capsmdb acase 10 f, 10 v capacitor 8 c50, c51, c53, c54, c63, c73, c83, c87 cc0402 cc0402 100 pf capacitor 2 c56, c62 cc0402 cc0402 1 nf capacitor 1 c59 capsmda acase 4.7 f, 6.3 v capacitor 4 c64, c75, c79, c82 cc0805 cc0805 7.5 pf, 1% capacitor 4 c65, c74, c80, c81 cc0805 cc0805 4.7 pf, 1% capacitor 1 c78 cc0402 cc0402 0.01 f capacitor 11 c84, c97, c98, c99, c100, c106, c108, c109, c111, c112, c114 cc0603 cc0603 0.1 f capacitor 4 c91, c92, c93, c94 cc0805 cc0805 dnp 2 c95, c96 cc0603 cc0603 dnp 1 c102 cc0402 cc0402 0.2 nf capacitor 2 c103, c104 capsmda acase 10 f, 10 v capacitor 1 c105 cc0805 cc0805 1 f ceramic capacitor 1 c110 cc0603 cc0603 470 nf capacitor 1 d1 panasonic lnj312g8tra 1.6 mm x 0.8 mm led-smd-tss-grn lnj312g8tra 1 d3 hsms-281c sot323-3 hsms-281c hsms-281c 1 j1 samtec ssw-120-02-sm-d-ra 40-pin through hole 40-pin right angle header female ssw-120-02-sm-d-ra/ samtec 6 j2, j3, j4, j5, j8, j11 smaedge smaedge dnp sma connector edge right angle 2 j6, j7 smaedge smaedge sma connector edge right angle 5 j10, s3, s5, s6, s11 smaupa04 sma200up sma connector rf 5-pin upright 5 s4, s8, s9, s10, s12 smaupa04 sma200up dnp 11 jp3, jp7, jp8, jp9, jp11, jp12, jp16, jp20, jp21, jp28, jp77 jprblk02 jprblk02 2-pin jumper header 10 jp6, jp10, jp15, jp22, jp26, jp29, jp54, jp78, jp88, jp89 jprblk03 jprblk03 3-pin jumper header 10 jp32, jp33, jp34, jp35, jp55, jp56, jp76, jp82, jp90, jp91 jprsld02 jprsld02 solder jumper
ad9114/ad9115/ad9116/ad9117 rev. a | page 76 of 80 qty reference designator device package description part no./ manufacturer 11 l1, l2, l3, l4, l5, l6, l7, l12, l13, l16, l19 ind1812 lc1812 exc-cl4532u1 exc-cl4532u1 4 l8, l9, l10, l11 ind1008 lc1008 1.8 h, 10% 4 l14, l17, l18, l20 ind1008 lc1008 dnp 1 l15 ind1210 lc1210 exc-cl3225u1 exc-cl3225u1 1 p1 usb-minib usb-minib usb mini 5-pin 1 p3 molex 0532610571 molex 0532610571 1.25 mm, 5-pin wire- to-board connector 0532610571/ molex 2 r1, r58 rc0805 rc0805 32 k, 0.1% resistor era6yeb323v, era6y 5 r2, r23, r25, r31, r36 rc0603 rc0603 76.8 k resistor 5 r3, r4, r5, r10, r29 rc0603 rc0603 78.7 k resistor 6 r6, r33, r34, r64, r65, r67 rc0402 rc0402 0 resistor 7 r17, r66, r68, r69, r107, r110, r122 rc0402 rc0402 dnp 1 r7 rc0603 rc0603 10 k resistor 5 r8, r12, r30, r32, r92 rc0603 rc0603 64.9 k resistor 8 r9, r37, r42, r56, r97, r98, r100, r101 rc0603 rc0603 dnp 4 r11, r38, r79, r83 rc0603 rc0603 0 resistor 4 r13, r14, r52, r53 rc0603 rc0603 dnp 10 r15, r16, r123, r124, r73, r74, r75, r78, r93, r94, r105, r106 rc0603 rc0603 0 resistor 6 r22, r54, r118, r119, r120, r121 rc0603 rc0603 dnp 1 r18 rc0402 rc0402 49.9 resistor 2 r19, r21 rc0402 rc0402 0 resistor 3 r20, r26, r80 rc0402 rc0402 dnp 2 r24, r61 rc0603 rc0603 1 k resistor 1 r27 rc0603 rc0603 1 m resistor 7 r28, r39, r40, r41, r44, r45, r103 rc0402 rc0402 22 resistor 4 r35, r55, r99, r102 rc0603 rc0603 100 k resistor 1 r43 rc0402 rc0402 0 resistor 8 r46, r47, r48, r62, r82, r86, r116, r117 rc0402 rc0402 0 resistor 2 r49, r59 rc0805 rc0805 16 k, 0.1% resistor era6yeb323v, era6y 2 r50, r57 rc0603 rc0603 453 resistor 2 r51, r60 rc0805 rc0805 8 k, 0.1% resistor era6yeb323v, era6y 3 r63, r113, r115 rc0402 rc0402 499 resistor 3 r70, r71, r108 rc0402 rc0402 10 k resistor 1 r72 rc0402 rc0402 25 resistor 2 r76, r77 rc0402 rc0402 1.8 k resistor 1 r81 rc0402 rc0402 4.12 k resistor 1 r87 rc1206 rc1206 0 resistor 2 r88, r89 rc0402 rc0402 0 resistor 2 r90, r109 rc0402 rc0402 dnp 1 r91 rc0805 rc0805 49.9 resistor 2 r111, r112 rc0603 rc0603 dnp 1 r114 rc0402 rc0402 15 resistor 2 rp1, rp5 rnetcts743-8 rnetcts743-8 dnp
ad9114/ad9115/ad9116/ad9117 rev. a | page 77 of 80 qty reference designator device package description part no./ manufacturer 2 rp3, rp4 rnetcts743-8 rnetcts743-8 22 resistor 2 sw1, sw2 keybdswg omronb3sg b3s-1100 push-button 4 t1, t2, t3, t6 adtl1-12 mini_cd542 dnp 1 t4 etc1-1-13 sm-22 m/a com etc1-1-13 etc1-1-13/ m/a-com 2 t5, t8 adt9-1t mini_cd542 adt9-1t adt9-1t/ mini-circuits 1 t9 jtx-4-10t mini_bh292 jtx-4-10t+ jtx-4-10t/ mini-circuits 16 tp1, tp3, tp17, tp18, tp19, tp20, tp22, tp25, tp26, tp30, tp31, tp34, tp35, tp38, tp44, tp45 loopmini loopmini white test point 4 tp32, tp33, tp36, tp37 loopmini loopmini dnp 8 tp5, tp8, tp12, tp13, tp16, tp24, tp39, tp42 loopmini loopmini red test point 1 tp2 loopmini loopmini dnp 12 tp4, tp6, tp7, tp9, tp10, tp11, tp14, tp15, tp21, tp23, tp41, tp43 loopmini loopmini black test point 1 tp40 loopmini loopmini orange test point 1 u1 40-lead lfcsp, ad9717 lfcsp040-cp1 40-lead lfcsp, ad9717 ad9717/ analog devices 5 u2, u4, u6, u7, u11 adp3334 8-lead soic adp3334 voltage regulator adp3334/ analog devices 1 u3 usb-pic18f4550-i/ml-nd qfn044p65mm-ep1 pic18f4550, microchip usb port chip qfn44 8x8mm pic18f4550 2 u5, u14 adg3304bruz 14-lead tssop adg3304, 14-lead tssop adg3304bruz/ analog devices 1 u8 74lvc1g34 sc70-05 sn74lvc1g34dck, ti buffer ti-dck = sc70_05 pkg 1 u9 adl5370 lfcsp024p5mm-ep1 adl5370acpz adl5370acpz/ analog devices 1 u10 ad9512 lfcsp048-cp1 ad9512bcpz ad9512bcpz/ analog devices 1 u12 osc-s1703 osc-s1703 dnp 1 u13 8-lead soic, ada4899-1 soic8-n-ep op amp, ada4899-1 ada4899-1/ analog devices 1 y1 abm3b-20.000mhz-10-1-u-t smd 3.2 mm 5.0 mm 20 mhz 300-8214-1-nd/ digi-key
ad9114/ad9115/ad9116/ad9117 rev. a | page 78 of 80 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 134. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9114bcpz 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 AD9114BCPZRL7 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 ad9115bcpz 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 ad9115bcpzrl7 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 ad9116bcpz 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 ad9116bcpzrl7 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 ad9117bcpz 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 ad9117bcpzrl7 1 ?40c to +85c 40-lead lfcsp_vq cp-40-1 ad9114-ebz 1 evaluation board ad9115-ebz 1 evaluation board ad9116-ebz 1 evaluation board ad9117-ebz 1 evaluation board 1 z = rohs compliant part.
ad9114/ad9115/ad9116/ad9117 rev. a | page 79 of 80 notes
ad9114/ad9115/ad9116/ad9117 rev. a | page 80 of 80 notes ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07466-0-3/09(a)

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